Mar 2020 – Aug 2021 · 1 yr 5 mos · Lund, Skåne County, Sweden

• Leading the SoC Design & Integration team for the Mid-Band 5G DFE product as per the defined DFT/VERIF/PD Team’s requirements while ensuring utmost quality.
• Contributing to a inhouse Spyglass design & verification working group for formulation and definition of methodology.
• Carrying one the key roles in Low Power Architecture/Design working group for exploration on architectural and implementation level aspects of various known low power techniques.
• Worked on integrating various sub-systems/IPs together and creating a signed-off (Lint, CDC & RDC clean) RTL delivery. Create top-level Pin Constraints and Timing Constraints before we Synthesize, Timing clean, Physical partition and Place using Vivado/Quartus, to eventually provide a bit-stream/netlist.

Jan 2008 – Feb 2020 · 12 yrs 1 mo · Noida, Uttar Pradesh, India

• Led DN’s (Digital Networking Group) SoC Logic/Integration Team: This team was primarily responsible for various Front-End functions Sign-Off for DN SoC, which included -
• ArchDef & Product Requirement List study and reviews, to have thorough understanding for implementation.
• IP selection and BOM creation, based on PRL/ArchDef.
• Pins definition/muxing, IO integration/implementation.
• Micro-Architecture creation for Verif/DFT/PD teams.
• Power Intent impledmentation by creating UPF/CPF at full chip level and delivering/maintaining it throughout the SoC lisfecycle, for Verif team & PD team.
• Arteris NOC & ARM Gaskets/Bridge generation & integration based on the requirement.
• Implement Clocking and Reset for the SOC based on different requirement from IPs, Cores and Interconnect.
• Full Chip SoC logic integration/partitioning and glue implementation.
• DFT logic (BIST, Scan wrapper) implementation with help of DFT team.
• Initial bring-up of basic Interfaces and Register access network on SoC level TestBench.
• Emulation based Full Chip SoC cleanup for Emulation model buildup.
• LINT, CDC (RTL, Gate-Level CDC and Power-Aware CDC), RDC, Glitch Analysis sign-off.
• Synthesis of each subsystem/platform/super & Implement pipeline/feedthrough feedback.
• Provide STA constraints and timing exceptions to PD team.
• Finally deliver a “Full Chip Integrated RTL design” to SoC Verif/PD/STA/DFT Team.
• Implement ECOs as per the PD team’s requirement and check formal equivalence using formality.
• Fully integrated SoC RTL TOP Delivery Scheduling based on project milestones and timelines, bug fixes/tracking & represent in Global Core team along with other functions.
• Post Silicon arrival interact/help in all queries/requirement of Validation team for debugging.
• Digital Networking Group’s Subject Matter Expert for:
• Low Power Design and Implementation using UPF/CPF.
• SoC Debug Architecture and its Implementation.
• LINT, CDC, RDC and Glitch Analysis sign-off.
• IP-XACT usage and implementation.

Dec 2004 – Dec 2007 · 3 yrs · Gurugram, Haryana, India

•  As a part of IP Design Team, we had the responsibility for exploring latest image compression standards like JPEG-2k, HD-Photo, JPEG-LS, etc. in order to develop them as an in-house Digital IPs to be used in HP printer SOCs.
•  JPEG Codec: With the JPEG Codec IP from third party, I was responsible for delivering the JPEG Compression Solution consisting of MCU generators, Protocol Converters and Memory Controller. Basic Synthesis and Unit level verification for the entire super was completed successfully.
•  JBIG: In-house development of the IP for JBIG Codec which has seen silicon and is deployed in HP low-end printers. This is a modular IP which can be configured as Decoder or Encoder or a Codec. I was responsible for RTL coding, Synthesis & IP Verification for various blocks of this IP. Support for SOC level verification was also in the charter.
•  MUSIC-T: This was a proprietary Codec standard developed in house. I was involved in writing the RTL for the peripheral block of the Encoder and the unit level verification of this block.

Jul 2001 – Nov 2004 · 3 yrs 4 mos · Greater Hyderabad Area

•  PCI EXPRESS Core: I was a member of the PCI EXPRESS core IP development team. Was responsible for delivering RTL for some sub-blocks of TX and RX core of the Data Link Layer, for the PCI EXPRESS endpoint and bridge.
•  PCIX-to-PCIX Bridge: I was the owner for the full chip netlist verification. I architected the CSR space for this bridge and wrote the RTL for the CSR block. This bridge can operate in transparent, opaque and non-transparent mode. Separate set of registers has been implemented for transparent and non-transparent mode. It can be configured through primary or secondary interface. Using the PCIX BFMs and Compaq PCIX core I did the Block level testing.
•  Online Insertion and Removal Controller: Our next generation HT-to-PCI/PCI-X Bridge has a feature of OIR i.e. online insertion and removal of a Port Adapter from a powered host. I did the RTL coding for the controller state machine. My RTL was totally bug less as validated by the verification team.
•  Full Chip Verification of Resilient Packet Ring Processor: Resilient Ring Engine can be configured for multiple topologies and protocols like metro network protocol and legacy protocol (SRP and RPR). Thorough knowledge of these protocols helped me in doing compliance and RTL verification of this chip, which contains 30 different blocks. I was the owner of the testing and verification of GFP and HDLC block. I wrote 350 test cases in Perl for GFP block and 200 test cases for HDLC block. Gate-netlist verification of GFP block in the Full Chip environment.
•  EEPROM Controller: The CSR registers of Resilient Packet Ring Processor are configured through PCI but can also be programmed through serial EEPROM. I did the verilog BFM code for the controller state machine that interacts with the serial EEPROM outside the chip and tested it by plugging it in the verification environment. This code was used in the full chip environment for testing.

Jan 2001 – Jun 2001 · 5 mos · Greater Hyderabad Area

• I joined as a Fresh Graduate in Avant!/Synopsys and was assigned to the Polaris Verilog Simulator for its maintenance and development.

Jul 2000 – Dec 2000 · 5 mos · Pilani, Rajasthan, India

• Got introduced to VLSI world and got inspired by Dr. Chandra Shekhar who was the head of VLSI Department in CEERI Pilani. Learned VHDL and created a behavioural code for UART. Also got exposure to basic RTL synthesis.