Subhash Sharma

Product Manager

Bengaluru, Karnataka, India17 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led multiple teams for successful project delivery.
  • Built co-design teams and developed workflows from scratch.
  • Recognized as Employee of the Year in 2020.
Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in ASIC and Physical Design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignAsicCo-designDesign Engineering

Other Skills

Generative AIStatic Timing AnalysisTiming ClosureFloorplanningTCLLVSRTL designEDAClock Tree SynthesisVLSISoCPrimetimeDRCDebuggingSemiconductors

About

Bangalore: 1. Built an R2G function for ISP IP (2022) and later grown to 90+ members for ISP, DISPLAY(2024) and Codec(2026). Leading multiple teams and functions to deliver couple of projects in a year. 2. Team function includes dedictaed synthesis, DFT insertion, quality checks, PPA, Physical design, STA sign-off off, PV. Extended scope for IR sign off in 2026. 3. Experience in mentoring/coaching and building the team. Earlier in Singapore: 1. Senior Program Manager of customer-ASIC projects with technical leadership of Physical design, Power integrity, Co-design, Physical verification, STA and Package. Employee of the year - 2020 Lead a team of 40+ people to deliver the project. Experienced in working with multiple customer on project deliverables. Actively Engaged in many projects RFP, RFQ and SoW preparation & presentation to customer. 2. Built a team for co-design from scratch , developed the flow and delivered 25+ projects successfully. Nominated for employee of the year - 2018 Experience in handling multiple stake-holders and cross-site engagement. 3. Experienced on working as hands on owner for macros, blocks, block coordination, top owner, flow owner and technical lead. Worked on more than 40+ projects TO deliverables.

Experience

17 yrs 7 mos
Total Experience
5 yrs 10 mos
Average Tenure
15 yrs 6 mos
Current Experience

Mediatek

4 roles

Senior Manager

Jun 2020 – Present · 5 yrs 10 mos

  • Leading multiple teams for IP R2G domain.
Generative AIPhysical DesignStatic Timing AnalysisASICTiming ClosureFloorplanning+12

Technical Manager

Promoted

Jun 2015 – May 2020 · 4 yrs 11 mos

  • Senior Project/Program Manager for multiple ASIC chips and direct interface to customer.
  • 1) Lead the technology development team for Wired-ASIC projects.
  • 2) Managed multiple customer across US/UK site for project delivery.
  • 3) Design complexity ranges from flat chip to SoC up-of area 400mmsq.
  • Currently managing a team of 15 to deliver the project.
  • 4/2017 - 3/2018
  • 1.Built a team of 12 people for deliverable of Co-Design projects for different product lines.
  • a) Developed the Co-Design Flow in ICC2
  • b) Communications across sites to Package Team/BU/PD/PI for deliverable and drive the issue to resolve
  • Others
  • 1. Hands On Experience for 12nm GPU Power Integrity.
  • 2. Flat Modem (4G CAT 6) Implementation of ~7M instance count with ~29 power domains
  • a) Hands on experience and co-work with other members to deliver the project and reduced area by 2.5%
  • 3.. ICC2 Flow Development and Integration for Advanced Nodes : Co-work with 2-4 resources around 1 year.
  • a) Automation of Block Level Summary, ICV Integration, POCV Integration, Merge Mode CTS, Complex UPF Handling etc.
  • b) Deployment of ICC2 block flow in more than > 100 block in 1 year 3 months span.
  • 5. Hierarchical Flow Development and Technical Support for various SOC in ICC
  • a) Co-worked with another one member cross site and SNPS to drive/closure of the ies for more than ~12 projects.
  • 6. ICC/ICC2 Tool Ownership for Installation, License Management etc.
  • a) License Cost Optimization with monthly estimation for each projects based on tech nodes.
  • 7. Vendor Main Contact Point for Technical Discussion and drive/closure of the issues to meet project schedule .
Physical DesignPower IntegrityCo-designPhysical VerificationSTAPackage+1

Staff Engineer

Jun 2012 – May 2015 · 2 yrs 11 mos

  • 1. Hierarchical SOC Implementation for , MT3363, Smartphone 8135E2, and LTE TK6291
  • 2. Hierarchical Methodology and Flow Development for Other Projects and Support local Singapore site ~13 projects in a 2014-H1'2015
  • 3. Sound knowledge and interest in complex CTS Structure Handling and UPF
Hierarchical SOC ImplementationCTS Structure HandlingUPFPhysical Design

Senior Physical Design Engineer

Jul 2010 – May 2012 · 1 yr 10 mos

  • Domain : DTV, Demodulator & Smart Phones.
  • 1. Block/Macro - Coordination
  • 2. Project Schedule Planning
  • 3. 8+ Block Implementation netlist to GDSII in 40-28nm techmology, Multi-Power Domain blocks : modem etc implementations
  • 4. Flat Chips : 3 complex Flat Chips Implementation (Instance Counts upto : 2.3M+)
  • 5. Automation : Blocks status update in XLS format through TCL etc.
  • Guarding creation in Laker through TCL etc.
Block CoordinationProject Schedule PlanningAutomationPhysical Design

Mirafra technologies

Design Engineer @ Qualcomm

Sep 2009 – Jul 2010 · 10 mos · Qualcomm, Bangalore

  • PD Support at Qualcomm
  • a) 1 Critical Block Implementation from netlist to GDSII in largest chip of Qualcomm at that time (overall die size : 149mm2, 45nm Technology). Instance Count : 1.2M+ , 119 SRAMS, Static IR/EM Fixes through Redhawk, Timing closed in 24 corners in Primetime, PV check through calibre
  • b) SRAM oriented block implementation in Low Power Chip from netlist to GDSII. Instance Count : 1M+, SRAM : 120, Tech : 40nm, Includes IR/EM Fixes in Redhawk & STA fixes in 64 corners in Primetime.
  • c) Automation for unique slew violation in TCL for Magma & Primetime.
  • d) DDR3IO Test chip (Tech : 28nm, Freq : 700Mhz) small block implementation, Assist Top Level STA Fixes, Database preparation for TOP Level for hard IP's.
PD SupportImplementationAutomationPhysical Design

Insilica semiconductor ltd.

Design Engineer

Aug 2007 – Nov 2008 · 1 yr 3 mos · Bangalore

  • Project Category: Image Process Application, Low Power Audio Decoder SOC at 130 - 90nm technology node
  • 1. 8+ Blocks and 10+ Macro implementation from netlist to GDSII including PV, STA.
  • 2. DataBase Preparation (Lib-Lef Volcano)
  • 3. Memory Compiler CCGEN Usage
  • 4. Automation (TCL) : Read the XLS file of IO Pads and Placed in APR, Window Based DRC Clean up, Level Shifter Logical Connection Check
Image ProcessingLow Power Audio Decoder SOCAutomationDesign Engineering

Education

Indian Institute of Technology, Bombay

M.Tech — Electrical Engineering

Jan 2005 – Jan 2007

University of Rajasthan

B.E. — Electronics & Communication

Jan 2001 – Jan 2005

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