Vinay Gattu

Software Engineer

Hyderabad, Telangana, India11 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

8+ years in semiconductor functional verification.
Expert in UVM and RTL verification methodologies.
Proven track record in improving testing efficiency.

Stackforce AI infers this person is a Semiconductor and Telecommunications Verification Engineer with extensive experience in functional verification.

Contact

Skills

Core Skills

Functional VerificationVerification Environment DesignSoc DesignAutomation

Other Skills

Active ListeningBody LanguageCC++Charismatic LeadershipCommunicationDigital Image ProcessingDigital Signal ProcessingElectrical EngineeringFPGAField-Programmable Gate Arrays (FPGA)Formal VerificationGERAN ProtocolsHTMLHector

About

"Break it to the core to make it achieve more." This has been my professional philosophy. Who am I, you ask? I am an unsympathetic workhorse, dedicating my time to dissecting and stress-testing the voiceless creatures called digital designs—forcing them to function exactly as they were intended to. And when these silent entities come to life and create wonders in the market, I take pride in working behind the scenes. In short, I am an architect's confidant, a designer's wingman, and management's bounty hunter. Yes, I am a functional verification hardware engineer in the VLSI domain. With 8+ years of experience in the semiconductor space, designing efficient verification environments for validating audio and graphics IP, I bring expertise in functional verification of RTL logic, UPF generation & power-aware simulations, and FPGA emulation.

Experience

Amd

4 roles

Member of Technical Staff

Jul 2024 – Present · 1 yr 8 mos

Senior Silicon Design Engineer

Promoted

Jan 2020 – Jun 2024 · 4 yrs 5 mos

Worked on the block level verification of the custom core using UVM test bench.
Worked on the verification of the debug unit associated with the custom processor.
Performed RTL linting of video encoders and decoders using Synopsys VC-Lint tool.

UVMRTL lintingSynopsys VC-LintFunctional VerificationVerification Environment Design

Design engineer 2

Promoted

May 2017 – Dec 2019 · 2 yrs 7 mos

Design Engineer 1

Jul 2016 – May 2017 · 10 mos

Rice university

Graduate Research Assistant

Jun 2015 – Dec 2015 · 6 mos · Rice University, Houston, TX

Collaborated with Prof. Lin Zhong and Clayton Shepard (doctoral student)
Worked on integrating Argos base station design to the Xilinx Zynq-7000 All Programmable SoC using ZC706 evaluation kit and various software tools (Matlab Simulink, Vivado IDE, and Xilinx SDK)

Qualcomm

Associate Engineer

Jun 2013 – Jul 2014 · 1 yr 1 mo · Greater Hyderabad Area

Worked as part of team that tested and approved functionally sound modem chips in mobile phones
Verified GERAN(GSM EDGE Radio Access Network) protocols on various modem chipsets like MSM 8974, MDM 9615, MDM 9625, MDM 9635, MSM 8926, MSM 8916 and MSM 8610
Assumed sole ownership of activities related to MDM 9635 chip within the team
Improved the efficiency of the automated testing procedures using Perl scripting language and in-house Qualcomm tools by 5%

PerlModem TestingGERAN ProtocolsFunctional Verification

Bharat petroleum corporation limited

Engineering Intern

May 2011 – Jun 2011 · 1 mo · Mumbai Area, India

Completed in plant training and project work at Bharat Petroleum Corporation Limited (BPCL), Mumbai refinery during the summer of 2011 and submitted a report on "Generation and Distribution of Electricity at BPCL, Mumbai refinery"