Prashanth R. — Software Engineer
M.Tech with 6 year's of experience in memory and custom layout design Working on TSMC 2nm Have worked on Samsung 4nm, TSMC 3nm 4nm technology nodes. Worked on SRAM & RF memory Skilled to draw area & routing efficient layouts with proper sharing of diffusions and with less parasitics Have knowledge of EMIR and their effects. Expert in solving DRC LVS DFM and ERC of leafcells and hierarchial layout
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in advanced memory layout design.
Location: Karimnagar, Telangana, India
Experience: 7 yrs 10 mos
Skills
- Memory Layout Design
- Layout Design
- Custom Layout Design
Career Highlights
- Expert in memory layout design across multiple technology nodes.
- Proficient in solving DRC, LVS, DFM, and ERC issues.
- Hands-on experience with advanced semiconductor technologies.
Work Experience
MediaTek
Memory Layout engineer (1 yr 7 mos)
Layout Design Engineer (3 yrs 11 mos)
Mirafra Technologies
Layout Design Engineer ll (3 yrs 11 mos)
Album Semiconductors
Memory Layout Designign Engineer (2 yrs)
SumedhaIT
Custom Layout Design Engineer (4 mos)
Education
Master of Technology - MTech at Vidya Jyothi Institute Of Technology
at Jyothishmathi institute of technological sciences
