Shaik Nadeem Ahmed

Software Engineer

Sri Potti Sriramulu Nellore, Andhra Pradesh, India4 yrs 5 mos experience
Highly Stable

Key Highlights

  • Experienced in Functional Verification and UVM methodologies.
  • Proficient in SystemVerilog and VLSI design.
  • Currently a Senior Silicon Design Engineer at AMD.
Stackforce AI infers this person is a Silicon Design Engineer specializing in VLSI and verification methodologies.

Contact

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)Systemverilog

Other Skills

VerilogVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)System on a Chip (SoC)Integrated Circuits (IC)Internet Protocol (IP)QuestaSimAccelerated vipAMBAAPBSerial ProtocolsCadenceAldecGitHubPython (Programming Language)

About

Tools Used : 1. Aldec Riviera Pro 2. Questa sim 3. Cadence GitHub profile : https://github.com/Nadeem-Ahmed-S

Experience

4 yrs 5 mos
Total Experience
3 yrs 4 mos
Average Tenure
1 yr 1 mo
Current Experience

Amd

Sr Silicon Design Engineer

Mar 2025Present · 1 yr 1 mo · Hyderabad, Telangana, India · On-site

Mirafra technologies

2 roles

Senior Verification Engineer

Promoted

Oct 2024Feb 2025 · 4 mos

Verification Engineer 1

Sep 2021Sep 2024 · 3 yrs

Universal Verification Methodology (UVM)Functional Verification

Qsocs technologies

Design Verification Trainee

Jul 2019Jan 2020 · 6 mos · Bangalore Urban, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilog

Education

Siddharth Institute of Engineering & Technology, Puttur

Bachelor of Technology - BTech

Jun 2015Apr 2019

Narayana Junior College - India

Intermediate Education(12th)

Jun 2013Apr 2015

S S Vivekananda High School

Secondary Education(10th) — None

Jun 2012Mar 2013

Stackforce found 100+ more professionals with Functional Verification & Universal Verification Methodology (uvm)

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