ATUL THAKUR, Ph.D.

Software Engineer

Bengaluru, Karnataka, India13 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RF/mmWave IC Design and Analog Circuit Design.
Led AMS verification for GPS project at MediaTek.
Designed innovative noise figure measurement setup at IIT Delhi.

Stackforce AI infers this person is a Telecommunications and Semiconductor expert with a focus on RFIC design.

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Skills

Core Skills

Rf/mmwave Ic DesignAnalog Integrated Circuit Design

Other Skills

EmxCadenceSystem VerilogAMS VerificationLayout DesignSPICEIntegrated Circuit DesignLaTeXMatlabXcircuitAdobe PhotoshopLinuxMicrosoft OfficeLecturingTanner EDA

Experience

13 yrs 2 mos

Total Experience

2 yrs 3 mos

Average Tenure

3 yrs 8 mos

Current Experience

Mediatek

Staff Engineer (RFIC/Analog IC Design)

Aug 2022 – Present · 3 yrs 8 mos · Bengaluru

Designed, optimized and characterized the Tx-Loopback (IRR & LOFT) calibration circuit for WiFi.
Worked on Tx chain (IQM, PA and PA-driver) linearity (HD3/CIM3/IP1dB/IIP3), AM-AM, AM-PM and other important specs.
Worked on the interstage baluns, and analyzed them with EMX sims.
Studied and analyzed HRM (Harmonic Reject Mixers).
Designing and optimizing Rx Front-end circuits.
Design and analysis of inductor using EMX sims.
Learned an intriguing effect about inductor tuning by EMF stealing/sharing.
RX-Top circuit design lead and MTB AMS verification lead for GPS project.
Did RX-Top design sims and wrote System-Verilog (wreal) models for RF modeling to support AMS Verification(GPS).
Designed, Optimised and Characterised the 3-stage power amplifier, PA for WiFi.

RF/mmWave IC DesignAnalog Integrated Circuit DesignEmxCadenceSystem Verilog

Globalfoundries

Principal Engineer-Design Engineering

Jun 2020 – Jul 2022 · 2 yrs 1 mo · Bengaluru

Designing benchmark RF and mmWave LNA circuits (one stage-two stage, folded cascode) in various technologies like 22FDx (FDSOI), 45RFe (PDSOI), 130NSX (RFCMOS), SiGe (45SG, 8XP, 8HP), 8SW, 9SW(SOI), etc.
Designing optimized passives (mostly inductors) around the LNAs and laying-out templates/padframe for the tape-outs.
Full-chip/co-sims for the LNAs using EM simulations (EMX) and Cadence-spectre.
Submitting test-plans and characterizing taped-out LNAs.
Doing MHC for the designed/fabricated circuits.
Working on customer queries and specifications.
HBM and CDM ESD design for LNAs.
Designed and characterized 16G SiGe LNA.

RF/mmWave IC DesignAnalog Integrated Circuit DesignEmxLayout Design

Indian institute of technology, delhi

Senior Project Scientist

Oct 2019 – May 2020 · 7 mos · Delhi, India

Designed few LNAs for NAVIC, an indegenious GPS, for ISRO at SCL-Mohali.

Synopsys inc

Sr. A&MS Design Engineer

Aug 2019 – Sep 2019 · 1 mo · Noida Area, India

SERDES

Nptel

TA for Analog Electronic Circuit

Jul 2018 – Oct 2018 · 3 mos · IIT-Delhi, funded by MHRD(MoE now)

RF/mmWave IC DesignSPICECadenceIntegrated Circuit DesignLaTeXLayout Design+3

Indian institute of technology, delhi

Researcher and Teaching Assistant

Aug 2014 – Jul 2019 · 4 yrs 11 mos · IITD · On-site

Teaching Assistant (TA) Work:
As a TA, I took Analog Electronics Lab. of 3rd year B.Tech. students for three consecutive years. My main motive was to make them familiar with SPICE coding and make them use it to their advantage while designing analog circuits. Next to make them design their circuits using hardware/on breadboard.
Ph. D. Work :
Worked in the field of Radio Frequency Integrated Circuit (RFIC) design, main motive is to design the asynchronous transceivers. For which system level modeling is done in the Matlab-Simulink. I have on-hand design experience on digital, analog, mixed signal and RF circuits. Few of them are- calibrated DACs, SAR-ADC, beta multiplier (for current biasing), one-two stage OP-AMP, LNAs (wideband, narrowband, single ended and differential), active balun, active-passive mixers (Gilbert cell), VCO, DCO, PLL, CDR.
Cadence Virtuoso (EDA tool) is used extensively for schematic and layout designs. I have worked on Mentor Pyxis and Tanner too.
Designed passives like twisted shape inductor and high density MOM capacitors using electromagnetic simulations in ADS Momentum.
For protocol design put little effort on NS2 (network simulator), not an expert but did analyze some protocols like IEEE 802.11, BMAC, SMAC, etc.
Matlab (Simulink) is used extensively for modeling purposes at system level.
Designed a noise figure measurement set-up at IIT-Delhi for LNA noise characterization done at -152dBm/Hz (spectrum analyzer noise floor at 900MHz) further shifted to -110dBm/Hz with a pre-amplifier.
Fundamental research on distributed beam-forming. Motivation was to lock two transceivers, each having separate clocks, near to 0-ppm of offset frequency.
Tools/ scripts used:
Eagle-CAD
Latex
X-circuit
X-fig
VHDL
H-SPICE
ng-spice
Tcl
Pearl

Thapar university

M.Tech Project and Teaching Assistant

Jul 2012 – Jun 2014 · 1 yr 11 mos · Patiala Area, India

I was a post-graduate student here and did my project on Calibrated DAC and SAR-ADC design.
As a TA, I took Analog IC design Lab of my junior PG students.