Mallikarjun S.

Software Engineer

Greater Delhi, Delhi, India6 yrs 10 mos experience
Most Likely To SwitchAI ML Practitioner

Key Highlights

  • 4+ years of experience in SoC validation.
  • Expertise in hardware emulation and debugging.
  • Strong collaboration with cross-functional teams.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in hardware emulation and SoC design.

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Skills

Core Skills

System On A Chip (soc)Hardware EmulationPower ManagementRtl DevelopmentData Structures

Other Skills

Intel ArchitectureEthernetCadence perspecTransactor IntegrationPCIePython (Programming Language)DebuggingZebuLauterbachTarmacTPIU (Debug)EmulationJoint Test Action Group (JTAG)VerdiField-Programmable Gate Arrays (FPGA)

About

Currently, I am working as a senior Validation Engineer at Intel corporation and pursuing a master's degree from the BITS, Palani. Completed my undergraduate from Delhi Technological University in the Electronics and communication. Having a 4+ years of experience in model build( HSLE,TLS,Co-emulation,VPs), testbench and testcases development for different SOCs (IA Server, IA client, Arm based Automotive). Delivering on responsibilities like reset bring up of whole SOCs, sub-system Xtor integrations and validations of IPs like PCIE, Ethernet, TAP, JTAG, TPIU, Tarmac, Power management using waveform debug methods. I am interested in working on RTL Debugs and designs. I have proved myself as collaborative and team player by working with various stakeholders( firmware, validation, performance etc. ) and clients. Demonstrated excellent communication skills by working in cross geo cross BUs projects. I enjoy resolving challenging issues and finding root causes of failures in SOCs.

Experience

6 yrs 10 mos
Total Experience
3 yrs 5 mos
Average Tenure
5 yrs 3 mos
Current Experience

Intel corporation

Senior Validation Engineer

Feb 2021Present · 5 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

  • Currently working as a Emulation Validation Engineer, Responsible for various sub-system level verification on emulation, Acquainted with various test generators like Cadence Perspec and internal tools.
  • Developing C-state Power management testcases on Intel Architecture and enabling reset bring-up of Compute Die, Micro-arch level debugs, HW-SW debugging.
  • First time enablement of UVM test Infra with veloce emulation platform.
  • Ethernet and PCIE Xtor integrations and bring-up on NIC.
  • Worked on NIC, server and client projects.
System on a Chip (SoC)Intel ArchitectureEthernetHardware EmulationCadence perspecTransactor Integration+3

Nxp semiconductors

Design Engineer

Jul 2019Feb 2021 · 1 yr 7 mos · Noida, Uttar Pradesh, India · On-site

  • Worked as an Emulation Engineer with following responsibilities -
  • 1. Responsible to deliver various zebu builds by working in collaboration with Synopsys.
  • 2. Successfully integrated and verified various transactors like MIPI DSI,TPIU TRACE, TARMAC, LTB JTAG t32, PFE ENET.
  • 3. Debug on various cortex ARM based SoCs for reset and clocking bring up and protocols like AXI,APB and IPS using Verdi.
DebuggingZebuSystem on a Chip (SoC)LauterbachTarmacTPIU (Debug)+4

3st technologies

Trainee

Jun 2018Jun 2018 · 0 mo · Noida, Uttar Pradesh, India · On-site

  • Digital design,
  • Verilog HDL,
  • Implementation on FPGA
RTL DevelopmentField-Programmable Gate Arrays (FPGA)RTL DesignVerilogRTL Coding

Coding ninjas

Trainee

Jan 2017May 2017 · 4 mos · Delhi, India · On-site

  • Got enrolled in Basics of C++ with Data Structures and Algorithms.
  • Learnt about Data structures Recursion, Time space complexity, OOPS, Linked List, Stack, Queue, Tree ,graphs etc.
Dynamic ProgrammingC++Data StructuresObject-Oriented Programming (OOP)

Winter trainee (ti cepd) texas instruments centre for embedded product design

Internship Trainee

Dec 2016Dec 2016 · 0 mo · Netaji Subhas Institute of Technology, Delhi · On-site

  • learned about:-
  • Embedded systems,
  • PCB development,
  • Circuit optimisation,
  • Communication protocols

Xplicatus

Hardware Designer

Jul 2016Aug 2016 · 1 mo

  • GSM based GPS vehicle Tracking system loaded with different sensors using ATMEGA328pu and Coordinates were shown on Website using IOT. Also made a PCB of Whole Setup

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Jul 2022May 2024

Delhi Technological University (Formerly DCE)

Bachelor’s Degree — Electronics and Communications Engineering

Jan 2015Jan 2019

Rajkiya Pratibha Vikas Vidyalya

Senior Secondary — Science

Jan 2013Jan 2015

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