Digvijay Patil

Software Engineer

Pune, Maharashtra, India11 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Functional Verification and SystemVerilog.
  • Strong background in Digital Design and VLSI.
  • Proven track record in the semiconductor industry.
Stackforce AI infers this person is a Digital Design Verification Engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystemverilog

Other Skills

Universal Verification Methodology (UVM)RTL DesignDigital ElectronicsPythonIntegrated Circuit DesignVerilogVHDLModelSimCPerlASICDebuggingEDAVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)

About

Experienced Digital Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Verification and Validation (V&V), Python, Perl, Debugging, and Functional Verification. Strong engineering professional with a Bachelor of Engineering (BEng) focused in Electrical, Electronics and Communications Engineering from Pune University.

Experience

Marvell technology

2 roles

Senior Staff Engineer

Promoted

May 2025 – Present · 10 mos · Pune District, Maharashtra, India

Functional VerificationSystemVerilogUniversal Verification Methodology (UVM)RTL DesignDigital ElectronicsPython+11

Staff Engineer

Apr 2022 – May 2025 · 3 yrs 1 mo · Pune District, Maharashtra, India

Samsung electronics

Associate Staff Engineer

Sep 2020 – Mar 2022 · 1 yr 6 mos

Collins aerospace

2 roles

Senior Electrical Engineer

Promoted

Jun 2018 – Sep 2020 · 2 yrs 3 mos

Electrical Engineer

Jul 2017 – Sep 2020 · 3 yrs 2 mos

Asiczen technologies

Digital Design Engineer

Jun 2015 – Jun 2017 · 2 yrs · Bhubaneswar

Maven silicon

VLSI Trainee

Jun 2013 – Nov 2013 · 5 mos · Bangalore

  • Advanced VLSI Design and Verification Training.

Education

Savitribai Phule Pune University

Bachelor of Engineering (BEng)

Jan 2009 – Jan 2013

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