Jaswanth kumar karnatakam — Software Engineer

With over 3.5+ years of experience in RTL design, I have developed and optimized PCIe soft-IP solutions for pre-silicon and post-silicon platforms at AMD, which captures, decodes and display PCIe packets by processing raw PHY-level data. it supports PCIe gen1 through gen5 and supports for x1, x2, x4, x8, x16 lanes. I have experience in designing test platforms to validate PCIe DUTs in prototyping, emulation, and simulation environments. I have also contributed to Aerospace and Defense projects, including designing TDMA protocols at MAC layer for advanced radio communication systems. skilled in RTL Design, Verilog, Lint, CDC, PCIe, AXI, Synopsys Verdi, TCL scripting, Zebu emulation platform, HAPS Prototyping platform,

Stackforce AI infers this person is a Semiconductor Engineer with expertise in RTL design and communication protocols.

Location: Hyderabad, Telangana, India

Experience: 4 yrs 8 mos