M Javed pasha — Software Engineer

As a Pre-Silicon Verification Engineer at Intel Corporation, I lead the verification of complex SoC designs using System Verilog, UVM, and VIP. I have over 10 years of experience in the semiconductors industry, working with various ON-CHIP bus architectures, such as AMBA 5 and ACE. I have also developed Verification IPs for AMBA 4 and AMBA 5 in System Verilog, and tested them using ARM CCI550/CCI400/CMN600/CMN700, Ethernet, PCIE, and UART protocols. I have a strong background in Assertion Based Verification and High Level Synthesis using SystemC. I have used different simulators, such as Cadence Ncsim and Xelium, Synopsys-VCS/DVE, IUS, Questa, and verification tools, such as Verdi, DVE, Xilinx ISE, and Design Compiler. I have also worked with RCS tools, such as Perforce and Clearcase. I hold a Master's degree in VLSI from Gokaraju Rangaraju Institute of Engineering & Technology, where I learned the fundamentals and applications of VLSI design and verification. I am passionate about learning new technologies and solving challenging problems in the verification domain.

Stackforce AI infers this person is a Pre-Silicon Verification Engineer with expertise in semiconductor design and verification.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 10 mos