Sanjay Bagali

Director of Engineering

Bengaluru, Karnataka, India15 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Physical Design and Verification.
  • Expert in Low Power Design methodologies.
  • Proficient in multiple scripting languages for automation.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Low Power Techniques.

Contact

Skills

Core Skills

Low Power Design

Other Skills

SRAM ModellingValidationSoCVLSIASICDRCPerlStatic Timing AnalysisVeritas Cluster ServerPower Management

About

Skills: Physical Design, Physical Design Verification, IR Drop analysis, Low power design, Unified Power Format(UPF), System Verilog. Tools : ICC,SOC Encounter, Calibre DRC, Calibre LVS, Milkyway, Laker, EPS, Spyglass LP, VCS. Scripting Language: TCL,PERL,Shell.

Experience

15 yrs 7 mos
Total Experience
5 yrs 2 mos
Average Tenure
12 yrs 8 mos
Current Experience

Mediatek

4 roles

Technical Manager

Promoted

Jun 2019Present · 6 yrs 10 mos

Staff Engineer (Physical Design)

Jun 2015Jun 2019 · 4 yrs

Sr. Physical Design Engineer

Promoted

Mar 2015Jun 2015 · 3 mos

Physical Design Engineer

Jul 2013Feb 2015 · 1 yr 7 mos

Open-silicon research pvt. ltd.

ASIC Design Engineer

Jun 2011Jul 2013 · 2 yrs 1 mo · Bangalore

Intel technology india pvt. ltd

Graduate Intern Technical

Aug 2010Jun 2011 · 10 mos

  • 1. Validation of low power management techniques for SoC
  • 2. SRAM Modelling and Validation

Education

RV College Of Engineering

M.Tech — VLSI & Embedded Systems

Jan 2009Jan 2011

SDM College of Engineering & Technology, Dharwad

B.E — Electronics & Communication

Jan 2005Jan 2009

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