Prashant Joshi

Software Engineer

Delhi, India6 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in IP Verification and Protocol Development.
Hands-on experience with Ethernet and eMMC protocols.
Strong background in VLSI Design and Machine Learning.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP and protocol development.

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Skills

Core Skills

Rtl VerificationEthernet Protocol DevelopmentVip Development

Other Skills

Ethernet ProtocolVerilogSystemVerilogUVMMachine LearningPower PlantsRenewable EnergyPower GenerationElectriciansPower DistributionVery-Large-Scale Integration (VLSI)CC++LINUXautocad

About

Senior Silicon Design Engineer at AMD in IP Verification. Skilled in C, Verilog, SystemVerilog & UVM and cocotb Methodology. Currently working in Server IP development. Skilled in Ethernet Protocol VIP Development in TSN and 5G implementations on DLL & Mac Layer. Hands-on experience of working in Verification IP of eMMC(SD/SDIO/UHS-II) Protocol and AXI4 Interconnect. IP Verification Environment Designer. Interested in R&D in field of VLSI Design, Computer Architecture and Machine Learning.

Experience

6 yrs 3 mos

Total Experience

2 yrs 1 mo

Average Tenure

3 yrs 7 mos

Current Experience

Amd

Senior Silicon Design Engineer

Sep 2022 – Present · 3 yrs 7 mos · Hyderabad, Telangana, India · On-site

Worked on RDMA protocol verification.

RTL Verification

Cadence design systems

Lead Software Engineer

Jan 2021 – Sep 2022 · 1 yr 8 mos · Noida, Uttar Pradesh, India · On-site

Worked as owner of TSN protocol family in Ethernet VIP Mac layer. Developed CBS, TAS, SyncE, AVTP-NTSC and ETS feature in Ethernet VIP. Gained hands-on experience in PTP and IET protocols also.

Ethernet Protocol Development

Mirafra technologies

Verification Engineer II

Dec 2019 – Dec 2020 · 1 yr

Worked as Support Engineer at Intel Corporation. Provided support for BMAN and Ace flows (Intel Proprietary tools ).

Synopsys inc

Post Graduate R&D Intern

Feb 2018 – Nov 2019 · 1 yr 9 mos · New Delhi Area, India

> Working as a VIP Development R&D Intern
> HDL: Verilog/SystemVerilog
> Verification Methodology: UVM
> Tools: VCS, DVE
> Protocol: eMMC, SD, SDIO
PREVIOUS
> Machine Learning( Natural Language Processing)
> Convolutional Neural Network for Sentence Parsing and Open Information Extraction
> Language: Python
> Library: Spacy