Apr 2025 – Present · 1 yr

Jun 2022 – Present · 3 yrs 10 mos

• Performed direct compiler elaboration (DCELAB) checks at both tile and container levels to ensure clean synthesis and integration readiness.
• Reviewed unloaded, undriven, and tie-off connectivity to catch structural issues early in the design cycle.
• Conducted MTBF analysis and sign-off, contributing to timing closure and robustness against metastability.
• Executed design and integration of AXI, SDP, and SSB repeaters, with a focus on functionality, power domain compliance, and protocol integrity.
• Handled RTL linting and debug, ensuring clean code and adherence to design guidelines.
• Implemented ECOs for logic fixes and late-stage updates, including fixes for VSI-reported issues related to repeaters and power domains.
• Contributed to repeater clocking architecture, optimizing latency and timing across interconnect paths.
• Utilized Tile Builder for modular RTL construction and Verdi for efficient debug and waveform analysis.
• Managed IP integrations, ensuring seamless connectivity and proper design behaviour within tile and subsystems.

Dec 2021 – Jun 2022 · 6 mos