Saurabh Sharma

Software Engineer

Bengaluru, Karnataka, India11 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5+ years in RTL front end design and verification
Expertise in FPGA design and board validation
Strong skills in UVM based Protocol Verification

Stackforce AI infers this person is a VLSI Engineer with strong expertise in FPGA and RTL design.

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Skills

Core Skills

Rtl DesignVerification

Other Skills

MIPI CSI-2MIPI D-PHY InterfaceMIPI DSI ReceiverHDMII2CSPIAXI4AXISAvalon Bus InterfaceNIOS-IIDDR3 MIGHLS Based DesignCVerilogVHDL

About

Technology driven professional with 5 years and 7 months of experience in RTL front end design, verification , simulation and board validation / debugging on FPGA. Experience in RTL Integration, UVM based Protocol Verification, SoC verification. Worked on PIPE5, DP/eDP , MIPI CSI-2, D-PHY, MIPI DSI Receiver, HDMI, PCIe IP, I2C, SPI, UART, AXI4, Avalon Bus interface, NIOS-II, DDR3 MIG Experience in HLS based design acceleration based on Xilinx platform.

Experience

11 yrs 2 mos

Total Experience

5 yrs 7 mos

Average Tenure

8 yrs 3 mos

Current Experience

Intel corporation

Graphics Hardware Engineer

Feb 2018 – Present · 8 yrs 3 mos · Bangalore

MIPI CSI-2MIPI D-PHY InterfaceMIPI DSI ReceiverHDMII2CSPI+20

Vvdn technologies

2 roles

VLSI ENGINEER

Jun 2015 – Jan 2018 · 2 yrs 7 mos

Handled responsibilities at various stages which includes understanding customer requirement, designing architecture, preparing milestones, FPGA part selection, RTL coding, simulation, synthesis, timing closure, STA, pin-planning, validation.
Skills gained : AXI4, AXIS, MIPI CSI-2 protocol, MIPI D-PHY interface, MIPI DSI receiver, HDMI, I2C,etc.
Good team player & possess excellent interpersonal communication skills.
Entrusted with the responsibility to lead a team.

AXI4AXISMIPI CSI-2 protocolMIPI D-PHY interfaceMIPI DSI receiverHDMI+3