KIRTI JAYBHAYE — Product Engineer
I am an experienced VLSI Engineer with expertise in ASIC Physical synthesis and low-power Synthesis for advanced technology nodes. My skills include Scan/DFT Insertion, PPA optimization, congestion debugging, and timing analysis/closure. Proficient in tools like Conformal Low Power (CLP), Conformal LEC, and Siemens Tessent TestKompress for ATPG, and fussion compiler (FC)/ Design compiler (DC) for synthesis, I focus on delivering efficient, high-performance designs. I have experience designing custom macro memory RTL with redundancy logic, optimizing scan chains, and improving latency. Proficient in Verdi and HSPICE for validation, I’m also interested in Physical Design, Synthesis, and STA opportunities to drive innovation in semiconductor technology. #rtl#synthesis#sta#asic#DFT#integration
Stackforce AI infers this person is a VLSI Engineer specializing in ASIC design and synthesis.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 7 mos
Skills
- Asic Physical Synthesis
- Low-power Synthesis
Career Highlights
- Expert in ASIC Physical synthesis and low-power synthesis.
- Proficient in multiple EDA tools for efficient design.
- Strong background in RTL design and validation.
Work Experience
MediaTek
ASIC Synthesis Design engineer (contractor) (2 yrs 1 mo)
SecureMachines
FPGA Design engineer (6 mos)
NVIDIA
ASIC Intern (11 mos)
Diesel Locomotive workshop
Summer Internship (0 mo)
Nuclear Power Corporation of India Limited
Summer Intern (0 mo)
Education
Master of Technology - MTech at Vellore Institute of Technology
Bachelor of Technology - BTech at Dr. Babasaheb Ambedkar Technological University, Lonere
Diploma at Institute of petrochemical technology LONERE
ssc at K.V. kanya vidhyalay panvel
