Suhas Bhat P N

Software Engineer

Karnataka, India26 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in EDA with extensive C/C++ experience.
Led optimization projects for ASIC and FPGA synthesis.
Strong background in low-power design techniques.

Stackforce AI infers this person is a highly skilled EDA engineer specializing in ASIC and FPGA synthesis.

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Skills

Core Skills

EdaLogic SynthesisFpgaProgramming Languages

Other Skills

C++Low Power SynthesisUPFHigh Level OptimizationCongestion OptimizationFPGA synthesisTechnology mappingTool infrastructureC programmingJavacsh/tcshPerlTclVerilogVHDL

About

Software programmer with vast experience in EDA industry. Programming experience mostly in C/C++ in Unix and Linux platforms. Has been an individual contributor and team/tech lead. Specialties: Programming Languages: C, C++, Java Scripting Languages: csh/tcsh, Perl, Tcl HDLs: Verilog, VHDL EDA Synthesis Tools: Synopsys Fusion Compiler, Synopsys Design Compier, Altera Quartus Synthesis(FPGA), Xilinx ISE Synthesis(FPGA) Low Power Intent: UPF FPGA Place and Route Tools: Altera Quartus, Xilinx ISE Formal Verification Tools: Formality Simulation Tools: VCS Internet programming: HTML, Java Script, CGI Version Control Tools: Perforce, Clearcase, CVS Code Quality Management Tools: Coverity, Rational Purify Plus, Valgrind

Experience

26 yrs 11 mos

Total Experience

13 yrs 5 mos

Average Tenure

21 yrs

Current Experience

Synopsys india pvt ltd

Sr Staff R&D Engineer

Apr 2005 – Present · 21 yrs

Involved in enhancing and maintaining different optimization engines of Synopsys' ASIC synthesis products Design Compiler and Fusion Compiler. Worked on various optimization areas like High Level Optimization, Low Power Synthesis using UPF, Mux/XOR Optimization, Congestion Optimization.

C++Low Power SynthesisUPFHigh Level OptimizationCongestion OptimizationEDA+1

Zeta infotech pvt ltd

Sr. R&D Engineer

Apr 1999 – Mar 2005 · 5 yrs 11 mos

Involved in enhancing and maintaining Synopsys' FPGA synthesis product. Dealt with different technology mappers and tool infrastructure issues. Specifically worked on developing synthesis solutions for Actel, Altera and Xilinx FPGAs.

FPGA synthesisTechnology mappingTool infrastructureFPGAEDA