Rakesh Madala

Director of Engineering

Bengaluru, Karnataka, India13 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in Silicon Physical Design at Google.
Strong background in ASIC and VLSI design.
Proficient in multiple hardware description languages.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.

Contact

Skills

Other Skills

Physical DesignStatic Timing AnalysisASICSynthesisVerilogStatic Low Power VerificationLow Power SynthesisUPFPerlVLSICVHDLSoCSystemVerilogEDA

Experience

13 yrs 4 mos

Total Experience

3 yrs 4 mos

Average Tenure

3 yrs 4 mos

Current Experience

Google

2 roles

Silicon Physical Design Manager

Promoted

Feb 2025 – Present · 1 yr 2 mos · Bengaluru, Karnataka, India

PD & Implementation Engineer

Nov 2022 – Jan 2025 · 2 yrs 2 mos · Bengaluru, Karnataka, India

Intel corporation

3 roles

Senior Engineering Manager

Promoted

Apr 2022 – Nov 2022 · 7 mos

Engineering Manager

Promoted

Apr 2019 – Mar 2022 · 2 yrs 11 mos

SOC Design Engineer

Jun 2017 – Mar 2019 · 1 yr 9 mos

Mediatek

2 roles

Staff Engineer

Jun 2016 – May 2017 · 11 mos

Senior Engineer

Jan 2015 – May 2016 · 1 yr 4 mos

Amd

2 roles

Design Engineer 2

Jul 2014 – Dec 2014 · 5 mos

Design Engineer 1

May 2012 – Jun 2014 · 2 yrs 1 mo

Education

National Institute of Technology Calicut

Master of Technology (M.Tech.) — Electronics Design and Technology

Jan 2010 – Jan 2012

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