Pradeep Bhagavatula

CEO

Bengaluru, Karnataka, India13 yrs 9 mos experience

Key Highlights

  • Expert in Static Timing Analysis and Synthesis.
  • Proficient in multiple Synopsys tools and scripting languages.
  • Strong background in ASIC and SoC design methodologies.
Stackforce AI infers this person is a VLSI design expert with a focus on ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisStaTop Level SynthesisSynthesisVerilog

Other Skills

Timing closureConstraints developmentSTA Post LayoutLow Power SynthesisDFTScan RearrangeRepartitioningModule level Synthesisscan stitchConstraining DesignTop-down Scan insertionAXI protocolVerilog HDLtest bench implementationLogic Synthesis

About

Post-layout STA, PnR, Physical aware Synthesis Tools Expertise: PT/PTSI, DCG/DCT ,Exposure to ICC2/Innovus Scripting Languages: TCL , SHELL

Experience

13 yrs 9 mos
Total Experience
2 yrs
Average Tenure
1 yr 7 mos
Current Experience

Confidential

Sr Staff

Oct 2024 – Present · 1 yr 7 mos

Wipro

Technical Lead

Mar 2023 – Oct 2024 · 1 yr 7 mos

Intel corporation

SoC Design Engineer

Jun 2021 – Feb 2023 · 1 yr 8 mos · Bangalore Urban, Karnataka, India

Qualcomm

Lead Engineer, Sr

Jun 2018 – Jun 2021 · 3 yrs · bangalore

  • STA, Timing closure
Static Timing AnalysisSTATiming closure

Tessolve

Senior Design Engineer

Nov 2017 – Jun 2018 · 7 mos · Bengaluru, Karnataka, India

Smartplay technologies - an aricent company

2 roles

Senior Engineer

Promoted

Apr 2016 – Oct 2017 · 1 yr 6 mos · Bengaluru Area, India

  • Top Level Synthesis/STA, Constraints development
Top Level SynthesisSTAConstraints development

Engineer

Sep 2014 – Mar 2016 · 1 yr 6 mos · Bengaluru Area, India

  • Responsibilities Synthesis, STA Post Layout
  • Tools- DCG, DCT, PT, ICC
  • Low Power Synthesis
  • DFT, Scan Rearrange and Repartitioning
SynthesisSTA Post LayoutLow Power SynthesisDFTScan RearrangeRepartitioning+1

Moschip semiconductor

ASIC Design Engineer

Aug 2012 – Aug 2014 · 2 yrs · Hyderabad Area, India

  • Top level and Module level Synthesis, scan stitch, STA
  • Constraining Design
  • Performing Synthesis at Module level and Bottom-up approach at Top level
  • Performing Top- down Scan insertion
  • Peforming Top and Module Level STA
  • Exposure to P&R, CTS
Top level SynthesisModule level Synthesisscan stitchSTAConstraining DesignTop-down Scan insertion

Moschip semiconductor

ASIC Engineer Trainee

Dec 2011 – Apr 2012 · 4 mos · Hyderabad Area, India

  • Study and understanding of AXI protocol
  • Implementation of AXI master controller in Verilog HDL
  • Verifying the design by test bench implementation
AXI protocolVerilog HDLtest bench implementationVerilog

Education

Jawaharlal Nehru Technological University

Bachelor of Technology (BTech) — Electronics and Communications Engineering

Jan 2008 – Jan 2012

SVKM's Narsee Monjee Institute of Management Studies (NMIMS)

Master of Business Administration - MBA — Leadership and Strategy & Operations and Supply Chain

Oct 2021 – Mar 2023

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