Tarun Perumalla

Software Engineer

West Godavari, Andhra Pradesh, India10 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC and VLSI design methodologies.
  • Proven track record in functional verification engineering.
  • Strong background in developing verification environments.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and VLSI design.

Contact

LinkedIn

Skills

Core Skills

AsicVlsiFunctional VerificationVerification EngineeringUvm

Other Skills

VerilogSystem VerilogCSemiconductorsSoCVHDLC++DebuggingICMatlabEmbedded SystemsLinuxCadence VirtuosoTanner ToolsAtlas

Experience

10 yrs 3 mos
Total Experience
3 yrs 5 mos
Average Tenure
7 yrs 5 mos
Current Experience

Intel corporation

2 roles

Emulation Engineer

Apr 2020 – Present · 6 yrs

VerilogSystem VerilogASICCSemiconductorsSoC+30

Core Verification Engineer

Oct 2018 – Mar 2020 · 1 yr 5 mos

Qualcomm

Verification Engineer

Oct 2016 – Oct 2018 · 2 yrs · Bangalore

  • Worked on functional validation of PLL, HSIO blocks like USB, PCIE.
  • Worked on GLS functional verification. SV-UVM
  • Functional coverage, assertions debug
SV-UVMFunctional coverageAssertions debugFunctional VerificationVerification Engineering

Stmicroelectronics

Internship

Jul 2015 – May 2016 · 10 mos · Noida Area, India

  • 1.Developing verification environments for AMS IPs from verification plan to the functional verification.
  • 2. Understanding UVM Methodology for verification.

Education

National Institute of Technology Rourkela

Master of Technology (M.Tech.) — VLSI and Embedded systems

Jan 2014 – Jan 2016

Andhra University

Bachelor's degree — Electronics and Communications Engineering

Jan 2009 – Jan 2013

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