Ishan Jain

Product Engineer

Jabalpur, Madhya Pradesh, India6 yrs 7 mos experience

Key Highlights

Over 4 years in Semiconductor industry
Expert in CPU Subsystem validation
Strong background in low-power validation techniques

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in CPU and low-power systems.

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Skills

Core Skills

Post-silicon ValidationLow-power ValidationPre-silicon ValidationSystem-level Validation

Other Skills

VerilogSystemVerilogUniversal Verification Methodology (UVM)VLSIDigital ElectronicsPythonStatic Timing AnalysisCARM assemblySilicon DebugTrace 32 Lauterbach DebuggerUVMC++Matlab

About

Welcome to my LinkedIn profile! I am Ishan, a Hardware Engineer with a Master's degree in Communication System Engineering from IIT (BHU) Varanasi and a Bachelor's degree in E&C from MANIT Bhopal. With 4+ years of experience in the Semiconductor industry, I specialize in pre- and post-silicon validation of CPU Subsystems. My dedication to delivering impactful results and driving positive change has been the cornerstone of my career. Committed to continuous learning and professional development, I stay abreast of the latest trends and advancements in the field to remain competitive in this ever-evolving landscape. I firmly believe in the power of networking and building meaningful connections. Let's connect and explore opportunities to collaborate and contribute to each other's growth and success!

Experience

6 yrs 7 mos

Total Experience

2 yrs 3 mos

Average Tenure

2 yrs

Current Experience

Amd

Senior Silicon Design Engineer

Apr 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Working as Senior Silicon Validation Engineer with the AMD PCQV team.
Focused on core-level validation and debugging of low-power features during post-silicon bring-up and stress regressions in PR phase.
SKILLS:
Leading validation of low-power states (C-states, P-states, S0ix, S3, S4) and active idle transitions for x86 server and client CPUs.
Developed end-to-end python-based automation suit for stress validation across multiple workloads, OS environments, and silicon revisions.
Debugged power-related issues including wake failures, retention bugs, and low-power entry/exit anomalies with firmware, architecture, and OS teams.
Enabled performance validation of core pipeline to detect inefficiencies, latency bottlenecks, and throughput regressions during early silicon bring-up.
Strong experience in post-silicon bring-up, scalable validation flows, and cross-team collaboration for issue resolution.

VerilogSystemVerilogUniversal Verification Methodology (UVM)VLSIDigital ElectronicsPython+3

Qualcomm

2 roles

Hardware Engineer

Jun 2021 – Apr 2024 · 2 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Worked as CPU Subsystem Validation Engineer with the Qualcomm SVE (System Validation & Emulation) team.
Responsible for system-level validation and debugging in pre-silicon emulation environments, as well as device-level validation in post-silicon.
SKILLS:
Bare-Metal validation of CPU Subsystem for Cortex-A and Cortex-M profile [Pre and Post Silicon Validation].
Directed and random Stimulus writing in C and ARM assembly for CPUSS validation.
Silicon Debugs in areas ranging from Cache, Coherency, Power Management, DVFS, Timers and System-level Performance.
Hands on experience with Trace 32 Lauterbach Debugger.
Architectural and Micro-architectural understanding of ARM IPs.

CARM assemblySilicon DebugTrace 32 Lauterbach DebuggerPre-Silicon ValidationSystem-Level Validation

Summer Internship

May 2020 – Jun 2020 · 1 mo · Bangalore Urban, Karnataka, India

Worked as INTERIM ENGINEERING INTERN with DV Team at QUALCOMM, Bangalore.
Supported UVM RLM test-bench development for low-power validation of ARM-based SoCs.
Gained hands-on experience with SystemVerilog, UVM, and low-power simulation methodologies.

SystemVerilogUVMLow-Power Validation