Sreenivas Machavaram

Director of Engineering

Bengaluru, Karnataka, India21 yrs 8 mos experience

Highly Stable

Key Highlights

20+ years of VLSI frontend experience.
Proven expertise in SoC and custom processor verification.
Strong leadership in managing large verification teams.

Stackforce AI infers this person is a Semiconductor Verification Specialist with extensive experience in SoC and ASIC design.

Contact

sreenivas.machavaram@gmail.com LinkedIn

Skills

Core Skills

Soc VerificationPost Silicon ValidationSilicon ArchitectureTeam LeadershipVerification EngineeringDesign EngineeringMemory Interface VerificationAsic EngineeringDft Implementation

Other Skills

Technical Product ManagementProject ManagementClosureTeam ManagementDFTPerlSVVMMFunctional VerificationDDR SDRAMCommunicationHVLProductivity ImprovementWritten CommunicationUniversal Verification Methodology (UVM)

About

Hands-on Verification Techno Manager with over 20+ years of experience VLSI frontend. Experience in RTL coding, IP/SS/SOC verification, low-power verification, synthesis, DFT, timing analysis, GLS, ATE tests, and formal verification. * Adept at multitasking and leveraging deep, overlapping experience across various domains to drive technical reviews and achieve verification closure. * Proven verification specialist in Xeon D server SOC, Custom ASIP (application specific Instruction set ) processors, DDR4, DDR5, LPDDR4, SOC security, secure boot, JTAG, and ARM CPU sub systems verification. * Skilled in System Verilog, VMM, and UVM methodologies. * Demonstrated ability to lead teams for large SOC and customer projects. * Strong expertise on Formal techniques in Control path, Data path and instruction set verification. * Expertise in Perl, Python and Val Automation

Experience

21 yrs 8 mos

Total Experience

6 yrs 10 mos

Average Tenure

1 yr

Current Experience

Intel corporation

2 roles

Design Verification Manager (Technical Director)

Promoted

Mar 2020 – Apr 2025 · 5 yrs 1 mo

Driving SoC TB development , verification, emulation and post silicon validation. Also processor instruction set, processor sub system verification. Leading DDR SS val CoE

Technical Product ManagementProject ManagementSoC VerificationPost Silicon Validation

Silicon Architecture Engineer

Nov 2014 – Mar 2020 · 5 yrs 4 mos

Through acquisition of LSI Axxia Group.

ClosureTeam ManagementSilicon ArchitectureTeam Leadership

Lsi corporation

3 roles

Verification & Design Engineer Staff

Apr 2013 – Nov 2014 · 1 yr 7 mos

Design, Verification, Synthesis, STA , DFT and GLS of multiple Embedded and Soft Modems
Work involved verification for modem IP, development of SV/ARM C/DSP assembly tests
IP integration, IO intersion, BiST insertion, Scan and JTAG, ATE, Functional and Parametric test development
Verification of Custom Application specific Instruction set processors, debug and trace, custom instruction set verification. work involved vmm based SV env, vip, tests and verification closure for multiple soc
Verification of different DDRss and associated encryption logic with 3rd party controller and PHY. DDR se supports DDR3,/4, LPDDR3/4. for multiple chips in axxia product line.
Verification of Secure boot, JTAG authentication, JTAG based functional tests( Daisy chain based tests for post silicon bring up)

DFTPerlVerification EngineeringDesign Engineering

Verif Design Engineer Sr

Apr 2010 – Mar 2013 · 2 yrs 11 mos

ClosureTeam ManagementVerification EngineeringTeam Leadership

Verif Design Engineer

Jun 2007 – Apr 2010 · 2 yrs 10 mos

ClosureTeam ManagementVerification EngineeringTeam Leadership

Qualcore logic

2 roles

ASIC Enginner

Jun 2004 – May 2007 · 2 yrs 11 mos

In Qualcore I worked as an ASIC Engineer. Initially, I started as a DFT Engineer where my responsibilities where mainly DFT implementation, Synthesis, Timing Closure.
Later I moved into Intruguard Devices ODC in Qualcore. I worked as a verification Engineer for an year and my Tryst with networking and verification of networking products started.
In Qualcore I worked on verification of IG2000, IG2200, Versatile System On Chip and SATA.

ClosureTeam ManagementASIC EngineeringDFT Implementation