Yogesh Kumar Musthyala

Software Engineer

Bengaluru, Karnataka, India12 yrs 11 mos experience
Most Likely To Switch

Key Highlights

  • Expert in Physical Design and Digital IC Design.
  • Proficient in Static Timing Analysis and RTL coding.
  • Strong background in ASIC and VLSI technologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignDigital Ic Design

Other Skills

RTL codingINTERPRETING THE TIMING REPORTSSTAPOWER PLANNINGStatic Timing AnalysisASICVLSITCLLogic SynthesisRTL designFunctional VerificationTiming ClosureDRCFloorplanningPrimetime

Experience

12 yrs 11 mos
Total Experience
2 yrs 1 mo
Average Tenure
2 yrs 4 mos
Current Experience

Mediatek

Senior Staff Engineer

Dec 2023 – Present · 2 yrs 4 mos · Singapore · On-site

Physical DesignRTL codingINTERPRETING THE TIMING REPORTSSTAPOWER PLANNINGDigital IC Design+16

Imagination technologies

Staff engineer ll

Apr 2022 – Sep 2023 · 1 yr 5 mos · Hyderabad, Telangana, India · On-site

Samsung r&d institute india

Staff Engineer

Jul 2020 – Apr 2022 · 1 yr 9 mos · Bengaluru, Karnataka, India

Alpsoft technologies pte. ltd.

Physical Design Engineer

Nov 2014 – Apr 2020 · 5 yrs 5 mos · Singapore

Synapse techno design innovations pvt ltd

Project Engineer

Jun 2013 – Nov 2014 · 1 yr 5 mos · Bengaluru Area, India

  • Physical design
Physical designPhysical Design

Rv_vlsi design center

ASIC Design Trainee Engineer

Sep 2012 – Apr 2013 · 7 mos · Banglore

  • BANGALORE

Education

RV VLSI DESIGN CENTER

DIPLOMA IN ASIC DESIGN — VLSI TECHNOLOGY

Jan 2012 – Jan 2013

PRINCETON COLLEGE OF ENGINEERING AND TECHNOLOGY

Bachelor of Technology (B.Tech.)

Jan 2008 – Jan 2012

RBVRR HIGH SCHOOL

SSC — ALL SUBJECTS

Jan 2005 – Jan 2006

Stackforce found 100+ more professionals with Physical Design & Digital Ic Design

Explore similar profiles based on matching skills and experience

TS

Tanmay Sahu

Physical Design Engineer

at Intel Corporation

Bhopal, India1 yr 10 mos exp
Sahil Srivastava

Sahil Srivastava

SoC Design Intern

at Intel Corporation

Delhi, India0 mo exp
DFTElectronic EngineeringDigital Electronics
Anantha Padmanabhan B M

Anantha Padmanabhan B M

Physical Design Intern

at Qualcomm

Thiruvananthapuram, India2 yrs 6 mos exp
Semiconductor Fabrication
Shridhar Alure

Shridhar Alure

Staff Physical Design Engineer

at MediaTek

Bengaluru, India5 yrs 8 mos exp
Physical DesignVLSI
Ashish Jaiswal

Ashish Jaiswal

Senior Engineer

at Qualcomm

Bihar, India6 yrs 1 mo exp
Cellular Communications5G New Radio (NR)System Testing
Himanshu Ranjan

Himanshu Ranjan

Accumulated Expertise

at Career-Wide Experience

India0 mo exp
Srikanth Vaggu

Srikanth Vaggu

RTL Design Engineer

at MediaTek

Bengaluru, India5 yrs 3 mos exp
RTL DesignProject ManagementSynthesisStatic Timing Analysis
Venkatramana Gajavelli

Venkatramana Gajavelli

Staff Engineer

at Qualcomm

Hyderabad, India11 yrs 8 mos exp
DDR Protocols