Srikanth Vaggu

Software Engineer

Bengaluru, Karnataka, India5 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Proven execution in RTL design and verification.
Strong project management and team leadership skills.
Hands-on experience with advanced EDA tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and verification.

Contact

Skills

Core Skills

Rtl DesignProject ManagementSynthesisStatic Timing Analysis

Other Skills

Cadence GenusCadence InnovusFormal Connection ChecksPhysical DesignPhysical SynthesisDesignCompilerDigital IC DesignCDCDesignRDCLintProject PlanningDFTSynopsys PrimetimeLogic Synthesis

About

PERSONAL AND PROFESSIONAL TRAITS: * Humble in Change & Bold in Action * * Looking to Help, Create and Implement solutions for a company, not to point out problems * * Team player with a hunter mentality and a never give up attitude * * Many people have good and great ideas, Execution is what matters and I do execution * SKILLS AND COMPETENCIES: * Team management :- I take pride in my ability to motivate ,coach and mentor teammates.no matter who is under my watch, my approach is always the same. * Project management and execution :- I have some good knowledge on how to design,plan, and direct a project. This includes all phases, including project scope definition, scheduling, execution and evaluation. A sampling of projects I have led and supported are included in the project section of my profile. * Testing and debugging of applications using simulation tools * Hands on experience in unit testing of Embedded and VLSI design applications * Sound understanding of study of specifications, requirement gathering, designing, integration, testing, documentation and support. If you believe that I can be of help to you or if you would like to learn more about me, please get in touch or connect.

Experience

5 yrs 3 mos

Total Experience

1 yr 9 mos

Average Tenure

3 yrs 9 mos

Current Experience

Mediatek

4 roles

RTL Design Engineer

Jul 2023 – Present · 2 yrs 9 mos

𝐏𝐫𝐨𝐣𝐞𝐜𝐭-𝟭 : 𝐑𝐓𝐋 𝐃𝐞𝐬𝐢𝐠𝐧, 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 & 𝐒𝐲𝐧𝐭𝐡𝐞𝐬𝐢𝐬 𝐨𝐟 𝐚𝐧 𝐒𝐨𝐂 𝐓𝐨𝐩 𝐈𝐏 𝐈𝐎 𝐏𝐢𝐧𝐦𝐮𝐱.
𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲 : Advanced Process Node
𝐎𝐛𝐣𝐞𝐜𝐭𝐢𝐯𝐞 :
Gather specifications from all subsystem owners and manage IOs according to design requirements.
Generate the RTL based on Spec and validate it, ensuring correctness through linting and sanity checks.
Verified design features & functionality via simulation with existing and custom test cases.
Oversaw synthesis and DFT insertion, maintaining quality through rigorous sanity checks.

Cadence GenusCadence InnovusFormal Connection ChecksProject ManagementPhysical DesignStatic Timing Analysis+12

Senior Engineer

Jul 2022 – Present · 3 yrs 9 mos

RTL Design and Integration

Synthesis & STA Engineer

Jul 2022 – Sep 2023 · 1 yr 2 mos

𝐏𝐫𝐨𝐣𝐞𝐜𝐭-𝟭 : 𝟓𝐆 𝐌𝐨𝐝𝐞𝐦 𝐟𝐨𝐫 𝐅𝐥𝐚𝐠𝐬𝐡𝐢𝐩 𝐒𝐦𝐚𝐫𝐭𝐩𝐡𝐨𝐧𝐞 𝐒𝐨𝐂.
𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲: Advanced Process Node 𝐈𝐧𝐬𝐭𝐚𝐧𝐜𝐞 𝐂𝐨𝐮𝐧𝐭: 2 Million 𝐒𝐑𝐀𝐌 𝐂𝐨𝐮𝐧𝐭: 123 𝐅𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲: 700 MHz
Executed the synthesis of a block-level partition and also performed various netlist sanity checks to ensure the quality of the design.
Achieved targets of Logic UR, SRAM UR and Metal Density.
Delivered high quality database to PD meeting targets of WNS and Congestion Max Hotspot
𝐏𝐫𝐨𝐣𝐞𝐜𝐭-𝟐 : 𝟓𝐆 𝐌𝐨𝐝𝐞𝐦 𝐟𝐨𝐫 𝐌𝐢𝐝-𝐑𝐚𝐧𝐠𝐞 𝐒𝐦𝐚𝐫𝐭𝐩𝐡𝐨𝐧𝐞 𝐒𝐨𝐂.
𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲: Advanced Process Node 𝐈𝐧𝐬𝐭𝐚𝐧𝐜𝐞 𝐂𝐨𝐮𝐧𝐭: 1.3 Million 𝐒𝐑𝐀𝐌 𝐂𝐨𝐮𝐧𝐭: 35 𝐅𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲: 1.1 GHz
Managed the synthesis of a block-level hard macro, which is timing critical and also Conducted various netlist sanity checks to ensure the quality of the design.
Achieved targets of Logic UR, SRAM UR and Metal Density.
Delivered high quality database to PD meeting targets of WNS and Congestion Max Hotspot.
Conducted Modem Top Netlist LEC, including RTL-to-Netlist and Netlist-to-Netlist comparisons, at various stages of the design flow, from synthesis to tapeout.
𝐏𝐫𝐨𝐣𝐞𝐜𝐭-𝟯 : 𝐈𝐧𝐟𝐫𝐚 𝐁𝐮𝐬 𝐟𝐨𝐫 𝐚 𝐍𝐨𝐭𝐞𝐛𝐨𝐨𝐤 𝐒𝐨𝐂.
𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲: Advanced Process Node 𝐈𝐧𝐬𝐭𝐚𝐧𝐜𝐞 𝐂𝐨𝐮𝐧𝐭: 1.5 Million 𝐒𝐑𝐀𝐌 𝐂𝐨𝐮𝐧𝐭: 64 𝐅𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲: 1.6 GHz
Led the synthesis of a block-level hard macro which is both timing and and congestion critical and also Conducted various netlist sanity checks to ensure the quality of the design.
Achieved targets of Logic UR,SRAM UR and Metal Density.
Delivered high database to PD meeting Project Targets of WNS and Congestion Max Hotspot.

LECCadence GenusCadence InnovusConformal LECPhysical DesignDebugging+16

Intern

Jan 2022 – Jun 2022 · 5 mos

𝐒𝐲𝐧𝐭𝐡𝐞𝐬𝐢𝐬 𝐚𝐧𝐝 𝐓𝐢𝐦𝐢𝐧𝐠 𝐂𝐥𝐨𝐬𝐮𝐫𝐞 (𝐒𝐭𝐚𝐭𝐢𝐜 𝐓𝐢𝐦𝐢𝐧𝐠 𝐀𝐧𝐚𝐥𝐲𝐬𝐢𝐬) 𝐈𝐧𝐭𝐞𝐫𝐧
𝐎𝐛𝐣𝐞𝐜𝐭𝐢𝐯𝐞:
To understand the full flow of Synthesis process and Various Quality-Checks Process.
To understand how are we making use of Advanced EDA Tools to implement the design across various technology nodes.
To understand the various techniques that can be applied to the achieve the desired area, power and performance metrics for a design.
To understand the art of checking the log files and reports of the tool flow.
To understand and troubleshoot the issues and errors we observe in process and how to proceed further by fixing them.
Learning Outcome:
Got insights into various Tool flows that are being used by the industry at various levels of VLSI Design Flow.
Got to Understand the full flow of Synthesis process.
Got to Understand the various techniques that can be used to achieve the required Power , Performance and Area Metrics for a design.
Got to Understand the various types of Quality-Checks that will be done on the design at various levels of design flow to ensure electrical, physical and logical correctness of the design before tape-out.
Got to Understand the way a project takes off and the various activities involved in delivering a project successfully by consistently meeting the deadlines.