sambit datta

Director of Engineering

Bengaluru, Karnataka, India14 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in SOC physical integration and floorplanning.
Led cross-functional teams in semiconductor projects.
Strong background in timing convergence and circuit design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SOC integration and physical design.

Contact

Skills

Core Skills

Physical DesignSystem On A Chip (soc)

Other Skills

Problem SolvingUnified Power Format (UPF)FloorplanningPhysical IntegrationFullchip IntegrationRDLBump planningPhysical VerificationInterpersonal SkillsHardware EngineeringPlace & RoutePresentationsCommunicationLeadershipLayout Versus Schematic (LVS)

About

Currently responsible for building SOC with cutting edge latest technologies in INTEL INDIA

Experience

14 yrs 9 mos

Total Experience

14 yrs 9 mos

Average Tenure

14 yrs 9 mos

Current Experience

Intel corporation

3 roles

SOC Full Chip Floorplanning and Physical Integration lead

Promoted

Mar 2019 – Present · 7 yrs 1 mo

Led full-chip integration activities (floorplanning, package co-design, bump planning , Die file design, RDL/Top Metal routing , FCL collaterals generation, Analog/FC clocking integration, physical verification ) collaborating with cross functional teams across geographies.
Currently serving as Tech lead for Full-chip Floorplan & SOC Physical Integration FCL, RDL, bump assignment.

Problem SolvingUnified Power Format (UPF)FloorplanningPhysical IntegrationFullchip IntegrationRDL+4

SOC Design Engineer ( STA)

Jul 2014 – Nov 2020 · 6 yrs 4 mos

Responsible for 14nm/10nm XEON SOC level Timing Convergence for multiple SOCs
Main Focus:
IO SPEC/Constraints generation for SOC PnR blocks
CLOCK coding for SOC level timing
Convergence of Functional and DFX timing across full-chip/sub-chip across all corners
Interaction with synopsys on critical Bug fixes
Expertise in high speed Latch based timing convergence
Responsible for timing/electrical rules/CTS quality sign off for partitions

SOC Design Engineer

Jul 2011 – Jul 2014 · 3 yrs

Currently working on Complex Multi-port Register File Design. Have worked on circuit design and simulations. Have also worked on Register File Automation.
Responsibilities include Transistor level circuit simulations, electrical verification using IR, EM, noise flows, verification of arrays using Static Timing analysis (STA), logical equivalency flows.