mahaboob patan

Software Engineer

Bengaluru, Karnataka, India17 yrs 9 mos experience
Highly Stable

Key Highlights

  • Over 13 years of experience in RTL2GDS flow.
  • Key technical leader in client and server class products.
  • Expertise in Full Chip Integration and physical layout verification.
Stackforce AI infers this person is a seasoned Physical Design Engineer specializing in semiconductor design and integration.

Contact

Skills

Core Skills

Full Chip IntegrationLayout Design

Other Skills

layout automationphysical design convergenceMicrosoft ExcelEngineeringManagementProject ManagementCustomer ServiceLeadershipCManufacturingResearchSystem on a Chip (SoC)

About

physical design and integration engineer with 13+ years of experience in RTL2GDS flow. key technical leader who worked on multiple client and server class of products. primary skills on Full Chip Integration, floorplanning, design planning, clocking and physical layout verification. worked on multiple dies ranging from few mm2 to few hundreds of mm2 in die size.

Experience

17 yrs 9 mos
Total Experience
10 yrs 9 mos
Average Tenure
7 yrs
Current Experience

Intel corporation

2 roles

Principal Engineer

Promoted

Jul 2025Present · 9 mos

senior soc design engineer

Apr 2019Jul 2025 · 6 yrs 3 mos

Intel

Design engineer

Jul 2008Apr 2019 · 10 yrs 9 mos

  • reponsible for layout automation and physical design convergence.
layout automationphysical design convergenceFull Chip IntegrationLayout Design

Education

B. M. S. College of Engineering

Master's degree — Computer Science

Jan 2007Jan 2009

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