Dilip Kashyap — Product Engineer
Semiconductor professional with experience in the field of signal and power integrity across multiple domains(Data Server, Interface IP, and Automotive) • System-level Signal Integrity of serial and parallel interfaces (3D-EM extraction and optimization of interconnects leveraging machine learning solutions, channel simulation with equalization, timing analysis with SIPI co-simulation) • System and chip-level power integrity at leading edge nodes till 18A (MiM optimization, CPM/CMM generation, power gate modelling, jitter transfer function accounting PSIJ, time and frequency domain correlation for complex multi-PHY configurations up to 16DDR5 instances on a single package) • Multi-die full system power delivery analysis i.e., VR+PCB+PKG+Interposer+Die(s) (early rail analysis till sign-off, Static and Dynamic IR drop, CPM/die-model generation for stacked dies, PGV generation, PCB/PKG decap optimization, temperature aware DC Drop analysis for PCB/PKG) EDA: Voltus, Totem, Redhawk-SC, Ansys EM-suite, Keysight ADS, Sigrity EM suite, HSPICE, and Spectre.
Stackforce AI infers this person is a Semiconductor professional specializing in power and signal integrity analysis.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 1 mo
Skills
- Power Integrity
- Signal Integrity
- Gigabit Ethernet
Career Highlights
- Expert in power and signal integrity analysis.
- Led advanced packaging initiatives for tier-1 clients.
- Developed innovative solutions leveraging machine learning.
Work Experience
Intel Corporation
Power Integrity Lead (1 yr 10 mos)
Cadence Design Systems
Principal Solutions Engineer - 3DIC/SIPI (2 yrs 2 mos)
Synopsys Inc
Signal and Power Integrity Engineer - II (1 yr 11 mos)
Aptiv
Electrical Analysis Engineer-Signal and Power Integrity (7 mos)
Molex
Electrical Engineer (2 yrs 3 mos)
Tata Consultancy Services
System Engineer (3 yrs 4 mos)
Education
B.E at B. V. Bhoomaraddi College of Engg. & Tech., Hubli