Kishorr M.

Software Engineer

Bengaluru, Karnataka, India10 yrs 3 mos experience
Highly Stable

Key Highlights

  • 7+ years in VLSI backend design.
  • Expert in DDR PHY implementation.
  • Proficient in RTL to GDSII backend flow.
Stackforce AI infers this person is a VLSI backend design engineer with expertise in physical design and implementation.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVlsi

Other Skills

DDR PHY implementationRTL to GDSIIRTLGDSIIASICMatlabMicrosoft OfficeCLayout DesignAnalog Circuit Design8051 AssemblyCMOSRTL DesignDigital IC DesignStatic Timing Analysis

About

Total 7+ year experience in VLSI backend design. Worked on synthesis, sta and lec for 2 years. Working on complete backend flow from RTL to GDSII. Physical Implementation of DRR PHY for different technologies and timing closure for same.

Experience

10 yrs 3 mos
Total Experience
2 yrs 9 mos
Average Tenure
1 yr 11 mos
Current Experience

Intel corporation

CPU Physical Design Engineer

May 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Synopsys inc

2 roles

ASIC Physical Design Engineer Sr

Promoted

Nov 2021 – May 2024 · 2 yrs 6 mos · Bangalore

  • Worked on DDR PHY implementation from RTL to GDSII
DDR PHY implementationRTL to GDSIIPhysical DesignVLSI

ASIC Physical Design Engineer

Jun 2018 – Nov 2021 · 3 yrs 5 mos · Bangalore

Microsemi corporation

Backend Implementation Engineer

May 2016 – Jun 2018 · 2 yrs 1 mo · Bangalore

Terminus circuits pvt ltd

Intern

Jan 2016 – May 2016 · 4 mos · Bangalore

Education

Vellore Institute of Technology

M.Tech — VLSI Design

Jan 2014 – Jan 2016

KITs college of engineering, Kolhapur

B.E — Electronics &Telecomm

Jan 2009 – Jan 2013

Dr. D.Y.PATIL Jr. college

HSC — SCIENCE

Jan 2009 – Present

DATTAJIRAO JADHAV ENGLISH SCHOOL

SSC

Jan 2007 – Present

Stackforce found 100+ more professionals with Physical Design & Vlsi

Explore similar profiles based on matching skills and experience

Pankaj Verma

Pankaj Verma

Design Verification Lead

at Accenture

Bengaluru, India25 yrs 2 mos exp
Functional Verification
Swapnil Vats

Swapnil Vats

Senior Staff Engineer/Manager

at Qualcomm

Noida, India14 yrs 6 mos exp
arun cs

arun cs

Senior Department Manager

at MediaTek

Bengaluru, India21 yrs 1 mo exp
CharacterizationASIC
Sudheendra Bhat

Sudheendra Bhat

Electrical Cadet

at Maersk Line, Limited

Karnataka, India9 yrs 9 mos exp
Ramesh Halli

Ramesh Halli

Senior Department Manager

at MediaTek

Bengaluru, India21 yrs 2 mos exp
Swetha Gunda

Swetha Gunda

Senior Technical Manager

at AMD

Bengaluru, India18 yrs 6 mos exp
VB

Vallabh Bodhane

Manager Layout

at AMD

Hyderabad, India17 yrs 8 mos exp
SP

Sravanthi Pedireddi

Technical Lead

at HCLTech

Bengaluru, India8 yrs 2 mos exp
SoC DesignASIC Design
Kishorr M. - Software Engineer | Stackforce