Ankit Bapna

Engineering Manager

Bengaluru, Karnataka, India14 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led development of industry-first DDR5 PHY.
  • Expert in Analog and Mixed Signal Design.
  • Strong leadership in engineering management.
Stackforce AI infers this person is a Semiconductor Engineering Manager with expertise in Analog and Mixed Signal Design.

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Skills

Core Skills

Analog & Mixed Signal DesignMemory Interface IpsAnalog Circuit Design

Other Skills

High Speed DDR/LPDDR DesignUCIe DesignTeam CollaborationDDR5 PHYHigh Speed DesignDigital ElectronicsCVLSIVerilogMicrocontrollersPhysical DesignCadence VirtuosoASICProgrammingEmbedded Systems

Experience

14 yrs 5 mos
Total Experience
3 yrs 7 mos
Average Tenure
4 yrs 1 mo
Current Experience

Intel corporation

Engineering Manager

Mar 2022Present · 4 yrs 1 mo

  • High Speed DDR/LPDDR & UCIe Design
  • Part of Team which developed DDR5 PHY for industries first MRDIMM product : https://www.intel.com/content/www/us/en/newsroom/news/new-ultrafast-memory-boosts-intel-xeon-chips.html#gs.iqjocj
High Speed DDR/LPDDR DesignUCIe DesignTeam CollaborationAnalog & Mixed Signal DesignMemory Interface IPs

Synopsys inc

2 roles

Manager, A&MS Circuit Design

Dec 2017Feb 2022 · 4 yrs 2 mos

Senior Analog Design Engineer

Jul 2016Nov 2017 · 1 yr 4 mos

Nxp semiconductors

Senior IO Circuit Design Engineer

Dec 2015Jun 2016 · 6 mos

Sankalp semiconductor pvt ltd

2 roles

Senior IO Circuit Design Engineer

Promoted

May 2014Nov 2015 · 1 yr 6 mos

IO Circuit Design Engineer

Jun 2011Apr 2014 · 2 yrs 10 mos

Ericsson

Intern

May 2010Jul 2010 · 2 mos

Education

Vellore Institute of Technology

B.TECH — Electronics & Communication

Jan 2007Jan 2011

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