Lochan Anil Vyas

Software Engineer

Bengaluru, Karnataka, India11 yrs 5 mos experience

Highly Stable

Key Highlights

8 years of expertise in SoC physical design.
Proven track record in power optimization and design methodologies.
Recipient of multiple awards at Intel for outstanding performance.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on SoC and physical design optimization.

Contact

Skills

Core Skills

Power OptimizationSystem On A Chip (soc)Physical DesignLibrary Preparation

Other Skills

Power AnalysisApplication-Specific Integrated Circuits (ASIC)TCLComputer-Aided Design (CAD)PerlPerl AutomationUnified Power Format (UPF)Synopsys toolsFloorplanningPlace & RouteDesign Rule Checking (DRC)Shell ScriptingBashVerilogC

About

Enthusiast hardware engineer, crazy about IOTs and wearable market. Over the past 8 years I have built strong experty in SoC - Physical design. I have vast experience in developing, deploying Tools and flows for different styles of design - Servers, Graphics, Client - SoC and IPs. I am good at coding languages like TCL-Tk/PERL and good at problem solving. I have received multiple Divisional and Departmental awards at Intel.

Experience

11 yrs 5 mos

Total Experience

9 yrs 1 mo

Average Tenure

2 yrs 4 mos

Current Experience

Amd

Member of Technical Staff

Dec 2023 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

SoC PD power lead with IODC group. Role includes SoC power optimization (dynamic and static) and power rollup. PPA analysis, Activity profiling, recipe preparation, trade offs - for PNR blocks.
Along with power I also work on Construction for high speed global clocks and simulations.
Mesh style, Htree , Binary tree , clock balancing with power & performance optimzation. I drive design to closure for both these aspect of SOC

Power AnalysisPower OptimizationSystem on a Chip (SoC)

Intel corporation

3 roles

SoC Design Engineer

Promoted

Jun 2018 – Dec 2023 · 5 yrs 6 mos

I am responsible for Tools, Flows and Methodologies for full chip design plan/floorplan and integration. In this role I have developed floorplan flows from scratch and provided end2end solutions for Graphics SoC team at Intel. I have also developed different solution for pin planning and feedthrough planning which helped SoC team to improve PPA and TAT for design.
I have good expertise in interconnect planning, repeater planning for complex SoCs.
I have also worked on 3D IC flows includes Construction, Verification till Sign off.
Done multiple tape-ins and support throughout critical milestones.

Application-Specific Integrated Circuits (ASIC)TCLSystem on a Chip (SoC)Physical Design

Component Design Engineer

Jun 2015 – Jun 2018 · 3 yrs

Joined Intel as RCG, I was part of product development solutions group.
Key role: Owning development and deployment of library preparation tool, flows and methodology for
Hard-IPs and standard cells
Description: As a part of my job, I owned library preparation tool, flows and methodology for different
technologies used across Intel. It includes flow development, validation using in-house regression system,
making releases periodically, providing support to a vast customer base which includes internal and
external Hard-IPs and standard cell teams.
Being flow owner for 2.5 years I have got an opportunity to work in multiple domains in backend like
automatic placement and routing, fill flows, DRC-LVS, sign-off flows (work related to Hips/std cells). Having
developed a generalized flow which caters to teams across all business units, from IoT devices, modems
to world class servers, I have dealt with plethora of problems types and it has helped me to come up with
quick and quality solutions. I have vast experience in different IP and library views generation and I have
also contributed to methodology for IP-QA system which we have

Computer-Aided Design (CAD)PerlPhysical DesignLibrary Preparation

Intern

Oct 2014 – May 2015 · 7 mos

Description: Worked on Synthesis and DFT – Scan, DFT netlist checker
Developed few DFT netlist checks (rules) during this period and deployed to existing system which was &
is used in ongoing projects, Developed multiple TCL & PERL based utilities like, QoR/Metric reporting,
Regression reports, mailing/coloring etc

TCLPerl Automation