Utsasarit Dutta

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience
Highly Stable

Key Highlights

  • M.Tech in VLSI from a reputed institution.
  • Experience as a Synthesis and STA Engineer at MediaTek.
  • Strong foundation in Static Timing Analysis and Floor Plans.
Stackforce AI infers this person is a VLSI Engineer with expertise in synthesis and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Static Timing Analysis

Other Skills

Floor PlansLogic SynthesisPhysical DesignLECCLPCadence VirtuosoLinux

Experience

2 yrs 9 mos
Total Experience
2 yrs 9 mos
Average Tenure
2 yrs 9 mos
Current Experience

Mediatek

2 roles

Synthesis and STA Engineer

Jul 2023 – Present · 2 yrs 9 mos · Bengaluru, Karnataka, India

Floor PlansStatic Timing Analysis

Intern

Aug 2022 – Jul 2023 · 11 mos · Bengaluru, Karnataka, India

Education

Amrita Vishwa Vidyapeetham

Master of Technology - MTech — VLSI

Aug 2021 – Jul 2023

Maulana Abul Kalam Azad University of Technology, West Bengal formerly WBUT

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jul 2016 – Jul 2020

Jhargram Kumud Kumari Institution

Apr 2008 – May 2016

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