Feb 2023 – Mar 2026 · 3 yrs 1 mo · Bengaluru, Karnataka, India · On-site

• Validated key features such as Pin Planner, Design Space Explorer, and RAM Inference across multiple Altera FPGA families to support Quartus tool releases.
• Contributed to the functional verification of various IP cores in the Quartus IP catalog, including on-chip memory, arithmetic, and DSP IPs.
• Expertise in writing synthesizable RTL and performing CDC analysis and Lint checks to ensure code quality and timing closure.
• Developed and verified RTL/IPs using industry-standard verification methodologies with extensive simulation and debug cycles.
• Integrated and validated designs on Altera FPGA platforms using Platform Designer, with experience in lab debugging tools like SiganlTap Logic Analyzer, ISSP and ISMCE.
• Provided validation support for timing and bitstream generation for Agilex 3, 5, and 7 devices across multiple series.
• Analyzed pseudo-random designs and simulation testbenches generated by the Coconut fuzzing tool for Altera devices in regression environments, aimed at verifying the Quartus Compiler.
• Performed formal verification of the Quartus tool's functional correctness using OpenCores designs across various flow stages using the OneSpin 360 FV tool.
• Managed and maintained version-controlled repositories using Perforce for collaborative development and code review.

Oct 2020 – Nov 2022 · 2 yrs 1 mo

• Developed pixel-streaming algorithms for the design and implementation of Computer Vision systems on FPGAs and ASICs.
• Worked on adding Multi Pixel support i.e., 2, 4 and 8 pixels per cycle to various IPs from Vision HDL toolbox to support higher resolution and high frame rate input: Color Space Converter; Histogram; Bilateral Filter; Gamma Corrector; Edge Detector; Median Filter and Chroma Resampler.
• IP verification: Positive and negative tests; HDL codegen tests; FIL tests; Performance tests
• Cosimulation verification; Resource utilization and timing analysis
• Prototyped and verified computer vision algorithms on Zynq-based hardware with real video I/O, accelerating simulation and validating system behavior on actual devices.

Jul 2019 – Oct 2020 · 1 yr 3 mos

• Engineering Development Group