Pragati Sure — Software Engineer
- knowledge on ASIC flow and the stages involved in physical design flow. -worked on partition placement planning on full chip layout, pin placement, -Full chip clock design planning of high speed deterministic clocks. -clock simulation -simulation and recovering latency of high frequency clocks by clocksim, pathsim -Low power methodology back end verification using vclp, spyglass LP. -block pnr flow for 10nm designs
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC design and verification.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 7 mos
Skills
- Asic
- Physical Design
- Clock Design
- Low Power Methodology
Career Highlights
- Expertise in ASIC physical design flow.
- Proficient in high speed clock design and simulation.
- Experience with low power verification methodologies.
Work Experience
Intel Corporation
SOC DESIGN ENGINEER (9 yrs 1 mo)
RV-VLSI VLSI and Embedded Systems Design Center
Physical Design Engineer Trainee (6 mos)
Education
PG deploma at RV-VLSI
Bachelor of Engineering (B.E.) at P D A College of Engineering, GULBARGA
