chandrakanth Siribattina

Software Engineer

Andhra Pradesh, India3 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in DFT methodologies and chip testing.
Hands-on experience with industry-standard DFT tools.
Committed to enhancing chip performance and reliability.

Stackforce AI infers this person is a Semiconductor Testing Specialist with expertise in DFT methodologies.

Contact

Skills

Core Skills

Dft

Other Skills

scan insertionATPGmemory BISTscan DRC violationscompression logicTetramaxZERO delay simulationsSDF based simulations

About

Experienced DFT Engineer with a passion for ensuring the quality and reliability of semiconductor chips. With a strong background in design-for-test techniques and hands-on experience with industry-standard tools, I am dedicated to optimizing chip testing strategies and contributing to successful product launches. My journey in the VLSI industry has equipped me with a deep understanding of scan chain insertion, ATPG, memory BIST, and other DFT methodologies. I try to keep myself up-to-date with the latest advancements in DFT and semiconductor testing, always seeking opportunities to learn and apply emerging technologies to enhance chip performance. Holding certifications in DFT Training from Chip Edge, I am well-equipped to tackle intricate challenges and drive chip testing excellence. As a DFT enthusiast, I am committed to harnessing my skills in ensuring chip functionality, minimizing defects, and contributing to the seamless integration of DFT processes within the overall chip design flow. Let's connect to explore how we can collaborate to elevate chip quality and reliability together."

Experience

3 yrs 5 mos

Total Experience

3 yrs 5 mos

Average Tenure

3 yrs 5 mos

Current Experience

Mediatek

DFT Engineer

Nov 2022 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India

Chipedge technologies pvt ltd

DFT Engineer

Dec 2021 – May 2022 · 5 mos · Bengaluru, Karnataka, India

Performed scan insertion by defining constraints and different configurations.
Analysed and fixed scan DRC violations.
Performed scan insertion with compression logic.
Generated ATPG test patterns for Stuck at and Transition faults models.
Generated Basic and fast sequential patterns using Tetramax.
Performed ZERO delay and SDF based chain and scan pattern simulations.

scan insertionATPGmemory BISTscan DRC violationscompression logicTetramax+3

Asian paints

Engineering trainee

Aug 2019 – Jan 2021 · 1 yr 5 mos · Patancheru, Telangana, India

Spare Parts' Ensuring the availability of 'Critical of equipment by making indents through SAP.
Managing the Maintenance Activities of Daily Asset carereports
Regularfollowupwithfittersandelectriciansweatherthegivenworkiscompletedasperthechecklistgiventothem.
Having knowledge on predictive and preventive maintenance system.
Managing the Maintenance Activities of Decorative Paint unit like MOTORS .
Operation & Maintenance of 33KV SUBSTATION, TRANSFORMERS, DIESEL ENGINES, UPS ,SOLAR PLANT, ELECTRICAL EQUPMENTS
Operation & Maintenance of Cooling Tower, Boiler, Thermopac, and Heater less Vaporization.
Supervision of Quality and Safety issues while carrying out thejobs.
Frequent follow-up with the contractor's to ensure timely handover ofequipment.
Execution of work is carried as per Asianpaints safety manual (workpermitSystem) to ensure safewor
Job Planning day to day activity & allocating man power.