Murali Krishna Korada

Software Engineer

Srikakulam, Andhra Pradesh, India6 yrs 9 mos experience

Highly Stable

Key Highlights

6+ years of experience in SoC level DFT.
Expert in DFT IP generation and ATPG.
Proven track record in SoC DFT design and validation.

Stackforce AI infers this person is a Semiconductor DFT Engineer with expertise in SoC design and validation.

Contact

Skills

Core Skills

DftAtpgSoc Design

Other Skills

ATPG coverage improvementCC (Programming Language)C++Cadence VirtuosoDFT IP generationEDTEXTEST stuck model ATPGJavaMatlabMicrosoft ExcelMicrosoft OfficeMicrosoft WordOCCSSN integration

About

I have 6+ years of work experience in SoC level DFT

Experience

Broadcom

IC Design Engineer 3

Jul 2025 – Present · 8 mos · On-site

Samsung semiconductor

Associate staff engineer

Apr 2023 – Jul 2025 · 2 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

I have worked on DFT IP generation and supported their integration at block and top level; Spyglass DFT checks and worked with designers to improve scannability; tessent based MBIST, EDT, OCC and SSN integration at block level; block level ATPG for stuck-at, transition, sram TD modes; ATPG coverage improvement; block level ATPG pattern simulations; retargeting block level patterns to SoC level; top level notiming and timing simulations; EXTEST stuck model ATPG; static and delay fault cell aware model UDFM ATPG pattern generation

DFT IP generationSpyglass DFT checkstessent based MBISTEDTOCCSSN integration+9

Intel corporation

Graphics Hardware Engineer

Jun 2019 – Mar 2023 · 3 yrs 9 mos · Bengaluru Area, India · Hybrid

I have worked on SoC DFT design and validation on discrete graphics SoCs. I have experience in pin-muxing design for testing, validation of PLL DFT, TAP and manufacturing reset bring up.

SoC DFT designvalidation of PLL DFTTAPmanufacturing reset bring upDFTSoC Design