Sougatam Das

Senior Software Engineer

Kolkata, West Bengal, India3 yrs 9 mos experience

Key Highlights

Expert in FPGA synthesis and optimization algorithms.
Strong background in signal processing and communications.
Proven track record at AMD and Intel in semiconductor industry.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in FPGA development and optimization.

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Skills

Core Skills

C++FpgaVhdl

Other Skills

VerilogSystemVerilogBashLinuxVivadoField-Programmable Gate Arrays (FPGA)QuartusIntel Quartus PrimeVCSModelSimPerforceSignal ProcessingMachine LearningRadio Frequency (RF)Python (Programming Language)

About

Currently working as a Senior Software Development Engineer at AMD, contributing to the development of the Vivado Logic Optimization tool. Previously served as an EDA Software Engineer at Intel Corporation, where I worked on Quartus synthesis tool development for Intel FPGAs. I hold an M.Tech in Communications and Signal Processing from the Indian Institute of Technology (IIT) Jammu.

Experience

3 yrs 9 mos

Total Experience

2 yrs 7 mos

Average Tenure

1 yr 2 mos

Current Experience

Amd

Senior Software Development Engineer

Mar 2025 – Present · 1 yr 2 mos · Hyderabad, Telangana, India · Hybrid

Building optimization algorithms in Vivado for efficient handling of memories, SRLs, buffers, inverters, and carry chains, improving design performance and area
Developed algorithm for merging BRAMs in logic optimization.
Developed algorithm for converting underutilized RAMB36 to RAMB18
Developed efficient combinatorial loop detection algorithm

C++VerilogVHDLSystemVerilogBashLinux+3

Intel corporation

2 roles

Software Engineer

Jul 2022 – Feb 2025 · 2 yrs 7 mos · Bengaluru, Karnataka, India

Worked in Memory Inferencing in Synthesis
Supported synchronous and asynchronous reset in FPGA memory blocks
Supported handling of initial values on FPGA memory block
Developed Clock Gating mechanism in FPGA RAM Blocks to save Dynamic Power Dissipation
Implemented filtering mechanism for Quartus messages
Debugs and fixes Simulation & Synthesis failures in various RTL based designs
Supported Synthesis of force statement in Quartus
Created regtests for verifying functional equivalence between the RTL & Synthesized Netlist

VHDLC++FPGAQuartus