Bekkam Satheesh

Director of Engineering

Hyderabad, Telangana, India13 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in RTL2GDS physical design flows.
  • Taped out over 20 SOCs across multiple domains.
  • Strong management experience with multiple design teams.
Stackforce AI infers this person is a VLSI design expert with extensive experience in semiconductor technology.

Contact

Skills

Other Skills

Timing ClosureLogic SynthesisPhysical DesignCC++LinuxTCLPerlVerilogSystem VerilogUVMFPGA PrototypingStatic Timing AnalysisVLSIFPGA

About

Technology professional with broad range of technical and management skills: • Currently working in HM PD Lead role for MsMs, Auto, Compute, wearable & IoT chips. • Working on latest nodes e.g. 2nm, N3E, 4nm, 5nm, 7nm, 8nm, 10nm and 11nm technologies • Expertise in RTL2GDS physical design flows and methodologies and STA closure. • Taped out 20+ SOCs including MSMs, Auto, Compute, wearable & IoT chips • Low power techniques PGV/UPF/CPF, Cross Power domain analysis, IR drop impact. • Multi-scenario, Multi-mode analysis, Hierarchical , ETM, GBA/PBA signoff methodologies, • Clock ECOs, Logical ECOs, Constraint management, skew balancing, setup/hold/DRC/power ECO techniques. • Management Experience of managing multiple physical design teams simultaneously for various projects. • Strong inter-personal, team building and motivation skills, building teams from scratch, Tracking and Resource Management • Great engagement and collaboration skills with stakeholders & peers across functional/geographical areas • Passion for innovation & extreme automation of CAD processes & methodologies with knowledge of Perl, TCL languages

Experience

13 yrs 2 mos
Total Experience
4 yrs 3 mos
Average Tenure
3 mos
Current Experience

Marvell technology

Senior Staff Manager

Jan 2026Present · 3 mos · Hyderabad, Telangana, India · On-site

Qualcomm

3 roles

Engineer, Senior Staff/Manager

Nov 2023Jan 2026 · 2 yrs 2 mos

Staff Engineer

Nov 2020Nov 2023 · 3 yrs

Lead Engineer, Sr

Mar 2018Nov 2020 · 2 yrs 8 mos

Smartplay technologies

Senior Engineer

Jan 2015Feb 2018 · 3 yrs 1 mo · Bengaluru Area, India

Tata consultancy services

Systems Engineer

Dec 2012Dec 2014 · 2 yrs · bangalore

Education

VNR Vignana Jyoti Institute of Engineering & Technology

Master of Technology (M.Tech.) — VLSI System Design

Jan 2010Jan 2012

Anurag Enginnering College, Kodad,AP

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2006Jan 2010

Sri Venkateshwara Junior College

INTERMEDIATE — MPC

Jan 2004Jan 2006

ZPHS THEEDED

S.S.C — 10th Class

Jan 2003Jan 2004

Stackforce found 100+ more professionals with Timing Closure & Logic Synthesis

Explore similar profiles based on matching skills and experience