karthik akarapu

Software Engineer

Hyderabad, Telangana, India13 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in UVM and SystemVerilog for verification.
Proven track record in semiconductor industry.
Strong background in quality assurance and debugging.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and ASIC design.

Contact

Skills

Core Skills

UvmVerification

Other Skills

DebuggingAutomationModelingVerilogPerlVLSIVHDLMicrocontrollersFPGAC++Xilinx ISECTesting

About

Experienced Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Computer Architecture, and Microcontrollers. Strong quality assurance professional with a Master of Technology (M.Tech.) focused in VLSI AND CE from IIIT HYDERABAD.

Experience

Micron technology

2 roles

Principal verification engineer

Promoted

Nov 2023 – Present · 2 yrs 4 mos · Hyderabad, Telangana, India

Staff verification Engineer

Aug 2020 – Nov 2023 · 3 yrs 3 mos · Hyderabad, Telangana, India

Xilinx

Senior Verification Engineer

Mar 2017 – Aug 2020 · 3 yrs 5 mos

Amd

Design Engineer 2

Jul 2013 – Mar 2017 · 3 yrs 8 mos · Hyderabad Area, India

Universal video decode IP verification Engineer :
Developed Block level test bench for Inverse Transform (IT) and motion prediction(MP) block using UVM verification methodology:-
As a part of this project a implemented different UVC's required for IT and MP blocks and developed virtual sequencer and Scoreboard.
VP8 Bitstream profiling :-
In this project i profiled syntax elements of vp8 open source bit streams and developed automation script to find the coverage of all syntax elements ,which will help to find the coverage holes ,
UVD IP verification and debugging:-
My role in this project is to integrate DRM module and porting of DRM test related test cases , Modeling of Latency of memories ,developing debug bus and Debugging.

UVMVerificationDebuggingAutomationModeling

Ibm

internship

Jan 2013 – Jul 2013 · 6 mos · Banglore

1)Behavioral modeling of Ser-Des Receiver analog blocks using verilog:- Modeled High speed serializer and De-Serializer analog blocks in verilog for fast simulation.
2)Automation of power file generation of Ser-Des IP using perl :-Automated power file generation ,which is used for power analysis of Ser-Des IP using perl.

VerilogPerl