Jeffin Jose

Software Engineer

Bengaluru, Karnataka, India9 yrs 7 mos experience
Highly Stable

Key Highlights

  • 6.5 years of experience in IP verification.
  • Expertise in System Verilog and UVM methodologies.
  • Strong background in CXL, AMBA APB, and JTAG protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on Functional Verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Functional Verification

Other Skills

Test PlanningDebuggingSystemVerilogTCLGitPDLPerlMicrosoft PowerPointResearchSocial MediaData WarehousingMicrosoft WordMicrosoft OfficeVerilogC (Programming Language)

About

Senior Pre-Si IP Verification Engineer with experience of 6.5 years . Sound knowledge in System Verilog, UVM, ICL/PDL testing and Perl programming with experience in CXL ,AMBA APB and JTAG Protocols.Completed Masters in Electronics Design & Technology from NIT Calicut .

Experience

9 yrs 7 mos
Total Experience
3 yrs 6 mos
Average Tenure
2 yrs 6 mos
Current Experience

Amd

Senior Silicon Design Engineer

Oct 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

Verification Engineer

Jun 2019 – Oct 2023 · 4 yrs 4 mos

Test PlanningDebuggingFunctional Verification

Graduate Intern

May 2018 – May 2019 · 1 yr

  • Pre - Si Verification
DebuggingSystemVerilogFunctional Verification

Ibm india private limited

Associate System Engineer

Dec 2014 – Sep 2016 · 1 yr 9 mos

  • Data Specialist -ETL Ab Initio . Experienced in Operational Acceptance Testing & Design of AI graphs

Education

NIT Calicut

Master's degree — Electronic Design & Technology

Jan 2017 – Jan 2019

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2010 – Jan 2014

Hill Blooms school

X11

Jan 2008 – Jan 2010

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