Sorabh Chawla

Director of Engineering

Bengaluru, Karnataka, India19 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

17+ years of VLSI design expertise.
Led CPU PD/STA teams with a focus on PPA.
Hands-on experience across RTL to GDSII flow.

Stackforce AI infers this person is a VLSI design expert with extensive experience in ASIC development and physical design.

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Skills

Other Skills

Cross-functional Team LeadershipSemiconductorsStatic Timing AnalysisMicroelectronicsDRCICLogic SynthesisSoCASICRTLFloorplanningMixed SignalVLSIPrimetimeTiming Closure

About

17+ years of experience in VLSI design mainly in RTL to GDSII flow of ASIC: Hands-on CPU PD/ STA lead with a deep understanding of the PPA obligations, timing, cross domain dependencies and timelines/deliverables. Developed multifaceted technical competent team. Fully hands on all aspects of RTL-GDSII flow – STA, PD, Synthesis, Constraints Extensive experience in – Place and Route/Implementation, Timing Constraints Development (creation), Synthesis, Timing Analysis and Closure, Floorplanning & IO-Planning, Power Planning, , IR drop Analysis and ClosureExposure to Low Power Technology, Low Power Checks

Experience

19 yrs 7 mos

Total Experience

4 yrs 10 mos

Average Tenure

9 yrs 9 mos

Current Experience

Qualcomm

4 roles

Senior Staff Manager / Enggg

Promoted

Jul 2025 – Present · 9 mos

Senior Staff Engineer

Nov 2024 – Dec 2025 · 1 yr 1 mo

Started a new journey in CPU Team at San Diego

Senior Staff Engineer/Manager

Promoted

Dec 2019 – Nov 2024 · 4 yrs 11 mos

Staff Engineer

Jul 2016 – Dec 2019 · 3 yrs 5 mos

Mentor graphics

Senior Application Engineer P&R

Dec 2013 – Jul 2016 · 2 yrs 7 mos · Noida Area, India

St microelectronics

2 roles

Technical Leader

Promoted

Apr 2011 – Nov 2013 · 2 yrs 7 mos

Senior Design Engineer

Sep 2010 – Mar 2011 · 6 mos

Physical Design Engineer in Computer & Communications Infrastructure Product Group, (CCI) at ST Microelectronics, Greater Noida, India

Texas instruments

Senior Physical Design Engineer

Jul 2006 – Sep 2010 · 4 yrs 2 mos

Worked on the various aspects of backend for wireless chips for leading mobile handset manufacturers worldwide
Major Focus has been in fields of Logical Synthesis, Floorplanning, power planning, IO-planning, Place and Route, CLP, Timing Closure(PT/PTSI) & Design Rule Checks (DRC).
Did backend in 90, 65,45nm technologies.
Well versed with Synthesis and have written constraints single handedly from design spec's
Did Floorplanning and, Power planning across multiple designs, with all designs having multiple power domain designs and RF radios
Handled placement for multiple designs and techniques to ease routing congestion
Did Static Timing Analysis (using Primetime including SI) on complex mixed signal designs having multiple clocks. Have a thorough understanding of STA.
Equivalence using LEC between RTL to Synthesis netlist and then to final backend netlist.
Worked with worldwide TI teams ( Israel/France/Dallas )
Mentoring colleagues in TI-France and TI-Israel who moved into physical design domain, from other domains.