Prakash Hadimani

Software Engineer

Bengaluru, Karnataka, India3 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Proficient in Physical Design and Verification.
  • Hands-on experience with VLSI methodologies.
  • Strong foundation in Electronics and Communication Engineering.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Verification.

Contact

LinkedIn

Skills

Core Skills

Physical VerificationPlace & Route

Other Skills

8051 MicrocontrollerCMOSDigital ElectronicsIremSemiconductorsStatic Timing AnalysisVery-Large-Scale Integration (VLSI)

Experience

Signoff semiconductors

2 roles

Physical Design Engineer I

Apr 2023 – Present · 2 yrs 11 mos · Bengaluru, Karnataka, India

Physical VerificationPlace & RouteStatic Timing AnalysisCMOSSemiconductors

Trainee

Aug 2022 – Apr 2023 · 8 mos · Bengaluru, Karnataka, India

Education

SJB Institute of Technology

Bachelor of Engineering - BE — Electronics and Communication Engineering

Aug 2019 – Jul 2022

Stackforce found 55 more professionals with Physical Verification & Place & Route

Explore similar profiles based on matching skills and experience

UD

Uday Dasari

Sr. Engineering Manager

at Google

Santa Clara, United States18 yrs exp
Low Power SystemsPhysical DesignSystem on a Chip (SoC)
Salahuddin .

Salahuddin .

Staff Engineer

at Qualcomm

Bengaluru, India9 yrs 6 mos exp
Physical DesignVLSI
Divya Gupta

Divya Gupta

Senior Staff Engineer

at 7Rays Semiconductors India Private Limited

New Delhi, India12 yrs 8 mos exp
High-speed Digital DesignPhysical DesignStatic Timing Analysis
Sneha Tutika

Sneha Tutika

SoC Staff Engineer

at Synopsys Inc

Hyderabad, India10 yrs 10 mos exp
Physical DesignVLSI
VS

Vinay Shivakumar

Engineering Manager

at Google

Bengaluru, India19 yrs 3 mos exp
Clock DistributionPhysical DesignTiming Closure
Rohan Pachange

Rohan Pachange

Senior Engineer

at Micron Technology

Hyderabad, India6 yrs 10 mos exp
Layout VerificationPhysical DesignProgram ManagementSemiconductor EngineeringTechnical Training
Dr. Rajesh Navandar (PhD in VLSI)

Dr. Rajesh Navandar (PhD in VLSI)

Technical Lead ( Training)

at eInfochips

Pune, India1 yr 9 mos exp
ASIC Physical DesignCMOS Circuit Design
Ajay Mishra

Ajay Mishra

Engineering Director Solutions Group

at Siemens EDA (Siemens Digital Industries Software)

Fremont, United States27 yrs 6 mos exp
Cross-functional Team LeadershipHigh Level SynthesisProduct Engineer Team FormationProduct Lifecycle ManagementRTL-to-GDSII Implementation