Pragdev Panda

Operations Associate

Bengaluru, Karnataka, India20 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Static Timing Analysis and DFT methodologies.
Led UPF development for complex Modem IPs.
Managed DFT strategies for low power 28nm designs.

Stackforce AI infers this person is a Semiconductor Design Expert with a focus on DFT and Timing Analysis.

Contact

Skills

Core Skills

Static Timing AnalysisDftUpf DevelopmentDft Strategy

Other Skills

ASICPrimetimeLow-power DesignLow Power MethodologyTiming Constraints DevelopmentSTAPower EstimationSCAN InsertionPower AnalysisDFT implementationSTA Constraints developmentEquivalence ChecksPLLSERDESVerilog

About

Proficient in Synthesis & Static Timing Analysis Domains. Timing Constraints Development & Custom Timing Check Specifications. Low Power Methodology, UPF development & Static Low Power QC. Exposure to PnR Flow & Methodology, PnR Quality Checks. Good Hands on Experience in DFT Domain.

Experience

20 yrs 6 mos

Total Experience

4 yrs 1 mo

Average Tenure

11 yrs 7 mos

Current Experience

Mediatek

2 roles

Department Manager

Promoted

Oct 2017 – Present · 8 yrs 6 mos

Static Timing AnalysisASICPrimetimeDFTLow-power Design

Project Lead

Sep 2014 – Present · 11 yrs 7 mos

UPF developmentStatic Timing AnalysisDFTLow Power Methodology

Broadcom india pvt ltd

Principal Engineer

Oct 2013 – Aug 2014 · 10 mos · Bangalore

(Moved to Broadcom as part of acquisition of Wireless Modem group of Renesas Mobile by Broadcom)
My responsibilities here includes UPF development for complex 28nm Modem IP as defined by the low power strategy. Ensuring the quality of this UPF which is used for PA Verification and Implementation Teams by necessary UPF verification/checks & review with concerned Design Teams.
I am also responsible for UPF based Synthesis, defining test clocking strategy , interfacing with SoC Team for implementing all test specific requirements & ensuring DFT readiness of the design. I also contribute to Constraints Development and Static Timing Analysis tasks.

UPF developmentStatic Timing AnalysisTiming Constraints Development

Renesas mobile india pvt ltd

Specialist, ASIC

Dec 2010 – Sep 2013 · 2 yrs 9 mos · Bangalore

Responsible for overall DFT Strategy, DFT Clocking Design, DFT Constraints, MBIST Insertion, SCAN/LBIST Insertion.
Also responsible for test constraints development, STA and review of timing reports.
Strategy to reduce test cost & meet low power requirements on 28nm wireless chip & multiple Modem IP versions. RTL Power Estimation using PowerTheater and PT-PX Netlist Level Power Estimation Runs for various Functional Scenarios.

DFT StrategySTAPower EstimationStatic Timing Analysis

Nokia india pvt ltd

R & D Engineer

Jul 2008 – Dec 2010 · 2 yrs 5 mos

As Senior DFT Engineer handled DFT specific Licensee requirements, SCAN Insertion, & DFT Clocking design. Also worked on TestMode constraints development,STA timing closure.,Spyglass Lint, MoreLint DFTChecks, Spyglass & Conformal CDC Runs. RTL Power Analysis and Power Minimization Techniques with PowerTheater and PT-PX for Netlist Level Power Estimation.

SCAN InsertionSTAPower AnalysisDFT

Open silicon research private limited

ASIC Design Engineer

Jul 2005 – Jun 2008 · 2 yrs 11 mos

DFT implementation on multi-million gate designs BSCAN/MBIST/SCAN and custom IP testing ( Serdes,PLL,Codec etc )
STA Constraints development for TestModes and PrimeTime Timing Analysis
Formality Equivalence Checks ( RTL-RTL & RTL-Gate )
Taped out 4 chips while at Open-Silicon

DFT implementationSTA Constraints developmentEquivalence ChecksDFT