VINAYAKUMAR B H

DevOps Engineer

Karnataka, India11 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Proficient in UVM and SystemVerilog for RTL verification.
Hands-on experience with design and verification of complex digital systems.
Strong problem-solving and teamwork skills in engineering projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in RTL design and verification methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

DebuggingScriptingUVMDesign and Verification of RAMDesign and Verification of FIFODesign and Verification of APBDesign and Verification of ALUDesign and Verification of ETHERNETARM ArchitectureSystem ArchitectureObject-Oriented Programming (OOP)Application-Specific Integrated Circuits (ASIC)PerlLinuxQuestaSim

About

Experienced RTL Verification Engineer Skilled in Universal Verification Methodology (UVM), SystemVerilog, RTL Design, and Scripting With Sound Knowledge of Controller, Proccessor, Bus Protocols and Digital Design Concepts.

Experience

11 yrs 11 mos

Total Experience

8 yrs 8 mos

Average Tenure

11 yrs 11 mos

Current Experience

Mediatek

Staff Engineer

Aug 2019 – Present · 6 yrs 9 mos · Bengaluru Area, India

Universal Verification Methodology (UVM)SystemVerilogDebuggingScripting

Rv-vlsi vlsi and embedded systems design center

Graduate Engineering Trainee

Feb 2019 – Present · 7 yrs 3 mos · Bengaluru, Karnataka, India

Trained as Frontend RTL Design and Verification engineer with System Verilog and UVM Concepts. Experience in Design and Verification of RAM,FIFO,APB,ALU and ETHERNET using SV UVM.

SystemVerilogUVMDesign and Verification of RAMDesign and Verification of FIFODesign and Verification of APBDesign and Verification of ALU+2