Naveen Bishnoi

CTO

Bengaluru, Karnataka, India14 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI design and physical implementation.
Proven track record in semiconductor industry.
Strong leadership in technical roles at Intel.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in VLSI and physical design.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

Physical Verification14nm16nm20nmPhysical Design ImplementationFull Chip40nmDesign and Implementation of 32-Bit High Speed Booth Wallace MAC UnitVHDLVerilogCC++JAVA(Core)VLSI EDA ToolsDesign Architect IC

Experience

14 yrs 9 mos

Total Experience

4 yrs 2 mos

Average Tenure

10 yrs 1 mo

Current Experience

Intel corporation

3 roles

Senior Technical Lead

Promoted

Jan 2023 – Present · 3 yrs 4 mos

Technical Lead

Jan 2020 – Present · 6 yrs 4 mos

CPU Physical Design Engineer

Apr 2016 – Present · 10 yrs 1 mo

Amd

2 roles

Sr Physical Design Engineer

Promoted

Feb 2015 – Apr 2016 · 1 yr 2 mos

Contractor

Mar 2013 – Feb 2015 · 1 yr 11 mos

Physical Design and Physical Verification for Blocks and SOC at 14nm ,16nm and 20nm.

Physical DesignPhysical Verification14nm16nm20nmVLSI

Sicon design technologies pvt. ltd.

Physical Design Engineer

Aug 2012 – Feb 2015 · 2 yrs 6 mos · Bangalore

Physical Design Implementation of Full Chip at 40 nm and below.

Physical Design ImplementationFull Chip40nmPhysical DesignVLSI

Wipro technologies

Physical Design Engineer

Aug 2011 – Aug 2012 · 1 yr · Bangalore

Physical Design Engineer

Education

Thapar Institute of Engineering & Technology

Master of Technology (M.Tech.) — VLSI Design and CAD

Jan 2009 – Jan 2011

Guru Jambheshwar University of Science and Technology, Hissar

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