Samarth Kathal

Software Engineer

Bengaluru, Karnataka, India8 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC design and verification.
Strong background in hardware security techniques.
Proficient in C++ and SystemVerilog for tool development.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in ASIC design and hardware security.

Contact

Skills

Core Skills

Application-specific Integrated Circuits (asic)C++Hardware Security

Other Skills

TessentSystemVerilogUPFDFDAltair FlowTracerConformal LECLECVCLPSDCStatic Timing AnalysisSpyglassXceliumMBISTAutomatic Test Pattern Generation (ATPG)Python (Programming Language)

About

DFT Engineer at Synopsys India. Bachelor of Technology in Electrical Engineering. IIT Gandhinagar Alumnus. Budding techie with a knack for learning. Autonomous vehicle enthusiast.

Experience

8 yrs 2 mos

Total Experience

2 yrs 8 mos

Average Tenure

4 yrs 11 mos

Current Experience

Google

Silicon Engineer

May 2021 – Present · 4 yrs 11 mos · Bengaluru, Karnataka, India

Application-Specific Integrated Circuits (ASIC)Tessent

Synopsys inc

3 roles

Research And Development Engineer II

Nov 2020 – May 2021 · 6 mos

Research And Development Engineer

Jun 2019 – Nov 2020 · 1 yr 5 mos

Technical Intern

Jan 2019 – May 2019 · 4 mos

Worked in the Low-Power R&D team in the Verification Group. Mainly dealt with the development and testing of VCS tool features and functional verification. Proposed, Implemented and Debugged optimization algorithms for existing and new VCS features. Tasks involved functional verification, C++ coding, debugging, (System)Verilog testcase and testbench development along with Power Intent Specification with UPF. Gained experience on large scale software development on Perforce.

C++SystemVerilogUPF

Texas a&m university

Research Intern

May 2018 – Jul 2018 · 2 mos · Texas, U.S.A.

The project involved ensuring hardware security by improving existing split manufacturing techniques. Advanced split manufacturing uses efficient (and tactical) layout and floorplanning to prevent reverse engineering of a chip design. The project dealt with parsing DEF, LIB and LEF files for benchmark designs (and corresponding technology library) and algorithm implementation in C++.

Indian institute of technology gandhinagar

Tutor

Jan 2017 – Jan 2018 · 1 yr

Served as a tutor in IIT Gandhinagar, peer-assisted learning program to help UG freshmen for Digital Circuits course and UG sophomores for Electronic Devices course. Was selected based on outstanding performance in stated courses.