Komal Kesarwani

Software Engineer

Hyderabad, Telangana, India8 yrs 10 mos experience

Most Likely To Switch

Key Highlights

8+ years in Semiconductor Industry
Expert in Timing Characterization and STA
Experience with cutting-edge technology nodes

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and circuit characterization.

Contact

Skills

Core Skills

Standard Cell CharacterizationQuality AssuranceAnalog And Mixed SignalStatic Timing Analysis

Other Skills

CMOSCircuitCadence VirtuosoVirtuosoStandard CellDigital Circuit DesignTimingcharacterizationCircuit DesignNLDMLVFIOPython (Programming Language)ElectronicsVery-Large-Scale Integration (VLSI)

About

Working as Sr. Silicon Design Engineer in AMD Hyderabad. I have experience in Timing characterization and STA Tool exposure: NANOTIME and SiliconSmart Previously Worked in Qualcomm and NXP (clients through Capgemini) Bangalore. Having experience in Analog & Mixed signal Characterization , Standard Cell and Memory Characterization. Having 8+ years of experience in Semiconductor Industry. Worked on cutting edge technology like 2nm, 3nm, 5nm for UCIE / LPDDR / HBM projects. My role included Netlist extraction ,Timing setup , Characterization (.lib generation) , Quality Assurance of standard cells and Analog & Mixed signal macros. Worked on NLDM / LVF libs.

Experience

8 yrs 10 mos

Total Experience

1 yr 5 mos

Average Tenure

2 yrs 6 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Nov 2023 – Present · 2 yrs 6 mos · Hyderabad, Telangana, India · On-site

Qualcomm (client)

Engineer-lll

Jun 2023 – Sep 2023 · 3 mos · Bengaluru, Karnataka, India · On-site

Worked on Memory Characterization & Apache Power Library

Nxp semiconductors ( client )

Standard Cell Design Engineer

May 2022 – May 2023 · 1 yr · Bengaluru, Karnataka, India · On-site

Capgemini

Professional - ll

Apr 2022 – Oct 2023 · 1 yr 6 mos · Hyderabad, Telangana, India

Worked on memory characterization and standard Cell Characterization (.lib Generation) and Quality Analysis of generated .lib
Tech node : 22nm, 16 nm and 5 nm

CMOSCircuitCadence VirtuosoVirtuosoStandard CellDigital Circuit Design+3

Synopsys inc

A&MS Circuit Design Engineer - ll

Jul 2018 – Mar 2022 · 3 yrs 8 mos · Bengaluru, Karnataka, India

Worked on Characterization and STA of A&MS macros using NanoTime & SiliconSmart tool in Synopsys, Bengaluru (July 2018 - March 2022)
Worked on NLDM, LVF .lib generation for multiple PVTs for cutting edge technology like 3nm, 5nm, 7nm .

CMOSCircuitCadence VirtuosoAnalog and mixed signalcharacterizationCircuit Design+8

Intel corporation

Library Design Engineer

Sep 2017 – Jul 2018 · 10 mos · Bengaluru, Karnataka, India

Worked on timing characterization of standard cell using Siliconsmart tool. (Sept 2017 to July 2018)
Netlist extraction ,NLDM & LVF .lib generation and Quality Analysis was done for different technology node.

CMOSCircuitStandard CellDigital Circuit DesignQuality AssuranceTiming+1