Jul 2017 – Aug 2019 · 2 yrs 1 mo

• Serializer / Deserializer for PCIe 5.0 + combo phy

Jan 2014 – Jul 2017 · 3 yrs 6 mos

• Adaptive clocking for AMD new generation CPU,GPU & APU
• Responsible for PLL wrapper & Digital Frequency Synthesizer macro architecture, RTL design ,circuit design & development for various technology node
• Leading a team of engineers on high-speed custom digital circuit designs with a focus on high performance & low power.

Nov 2010 – Dec 2013 · 3 yrs 1 mo

• Responsible for design, development and analysis of high performance microprocessor clock distribution macro's
• Owner of Digital Frequency Synthesizer for 28nm AMD products.

Sep 2010 – Nov 2010 · 2 mos · Bangalore

• Supported multiple MNC semiconductor companies in Bangalore for the various tools/flows from Fishtail-DA .Demonstrated the new features added in the newer version of tool to the customers & help them building higher confidence on their Design Constraints .

May 2006 – Sep 2010 · 4 yrs 4 mos

• Responsible for Developing methodology for STA/SSTA-able compiler Embedded SRAM (ESRAM) at Texas Instruments .
• Also working on various aspectes of memory compiler verifications (including timing, logic )
• Responsible for Advance Statistical STA flow developments & tool qualification

Jan 2006 – Jan 2009 · 3 yrs

• Worked on Various aspects of testing and verification of SSTA tool from synopsys Prime Time VX , including accuracy , run time , analysis and other features like interconnect variation , Voltage & Temperature scaling effect . Delivered flow to setup SSTA analysis for IP design teams for migrating from STA to SSTA with ease of use . Also help the Design team in understating and interpreting the various effect of Process Variation on their design timing closure.

Jun 2005 – May 2006 · 11 mos

• Development and Implementation of Algorithms for Memory circuit optimization.
• The developments are done using Mat lab and the implementation is done using Perl.
• The tool is designed to help the circuit designer in getting a good starting point to meet their spec for the circuit in terms of timing with lesser effort and use lesser resource.

Dec 2003 – Jun 2004 · 6 mos

• Development of Avionics for the Advanced Fighter Planes.
• FPGA/CPLD based platform for the implementation of Avionics.
• Used VHDL for modeling and Xilinx tool for synthesis of logic & tested using Vertex IV FPGA.

Dec 2001 – Aug 2002 · 8 mos

• Responsible for block Level Layout design of Mixed Signal Components like DAC/ADC ..etc.
• This includes the Layout verification
• Layout creation
• Geometric verification of Layout.
• Creation of back annotated netlist from the layout for spice simulation
• Also responsible for standered cell Design , layout & verification

Jun 2001 – Sep 2001 · 3 mos

• At Centre For Electronics Design & Technology of India ( currently known as DOEACC ) the project was development of Data Acquisition system for water level monitoring in reservoir. The system is build around micro controller and peripheral systems consists of various sensors, data converters and controllers to take measurements of water level at various interval of time and transfer the data to a PC so as to analyze the data.