Shreyana S

Software Engineer

Bengaluru, Karnataka, India4 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Automatic Test Pattern Generation (ATPG)
  • Proficient in DFT methodologies and tools
  • Experience with cutting-edge 3nm and 2nm technology
Stackforce AI infers this person is a DFT Engineer with expertise in semiconductor testing and verification.

Contact

LinkedIn

Skills

Core Skills

Automatic Test Pattern Generation (atpg)DftSpring BootPython (programming Language)

Other Skills

Simulation

About

Automatic Test Pattern Genaration (ATPG), Scan-Compression, EDT, Gate level simulation, ATPG DRCs, Debug test-coverage and also debug simulation mismatches. Worked on EDT tools like Tessent Shell, TestKompress, Synopsys VCS, Verdi, Xcelium Cadence, DVE. Worked on 3nm and 2nm technology on SoC with SSN based architecture.

Experience

4 yrs 4 mos
Total Experience
3 yrs 3 mos
Average Tenure
4 yrs 4 mos
Current Experience

Mediatek

DFT Engineer

Feb 2024 – Present · 2 yrs 3 mos · Bengaluru, Karnataka, India

Automatic Test Pattern Generation (ATPG)DFT

Infosys

System Engineer

Jan 2022 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India

Spring BootPython (Programming Language)

Education

Malnad College of Engineering, HASSAN

Bachelor of Engineering - BE — Electronics and Communications Engineering

Jan 2016 – Jan 2020

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