Shivakumar Revanna — Product Engineer
Seventeen plus years of Design For Test experience. Expertise with Mentor Graphics tools. Areas of expertise include: Automatic Test Pattern Generation (ATPG), Design Rule Checking (DRC), Test Coverage Analysis, Timing exception handling in ATPG, Test Pattern Verification and Debug, Silicon failure diagnosis. JTAG pattern generation, Knowledge on BIST logic. Objective is to be a DFT Engineer, an individual contributor, and preferably involved in test pattern development.
Stackforce AI infers this person is a Semiconductor DFT Engineer with extensive experience in ATPG and BIST tools.
Location: Bengaluru, Karnataka, India
Experience: 20 yrs 9 mos
Skills
- Atpg
- Dft
Career Highlights
- Over 17 years of Design For Test experience.
- Expertise in Automatic Test Pattern Generation and BIST.
- Proven track record in customer support for DFT tools.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Design For Test (3 yrs)
Intel Corporation
Design For Test (1 yr 7 mos)
Mentor Graphics
Sr. Corporate Application Engineer - Design For Test (13 yrs 5 mos)
Wipro Technologies
Project Engineer (2 yrs)
DiagnoSYS
Development Engineer (1 yr)
Education
B.E at RV College Of Engineering
PGD at Sandeepani School of VLSI Design
