RUCHIKA PARATE

Software Engineer

Bengaluru, Karnataka, India6 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in DFT methodologies and tools.
  • Proficient in ATPG and simulation techniques.
  • Strong background in scan insertion and debugging.
Stackforce AI infers this person is a DFT Engineer with expertise in VLSI design and testing methodologies.

Contact

LinkedIn

Skills

Core Skills

SimulationSpyglass Dft For Rtl

Other Skills

netlistSpyglass DFT for RTL and netlistAutomatic Test Pattern Generation (ATPG)atpg simulation

Experience

6 yrs 5 mos
Total Experience
1 yr 11 mos
Average Tenure
4 yrs 6 mos
Current Experience

Einfochips (an arrow company)

Sr. DFt Engineer

Nov 2024 – Present · 1 yr 6 mos

Cerium systems

DFT Engineer

Nov 2021 – Present · 4 yrs 6 mos · Bangalore Urban, Karnataka, India

SimulationSpyglass DFT for RTLnetlist

Mediatek

DFT Engineer

Mar 2021 – Oct 2021 · 7 mos · India

Skandysys private limited

DFT Engineer

Jun 2019 – Oct 2020 · 1 yr 4 mos · Bengaluru Area, India

  • Experienced on Mentor and Synopsys tools in Scan Insertion, ATPG, solving DRCs,Coverage Analysis and debugging, no-timing simulation, JTAG,MBIST

Vlsiguru training institute

DFT Trainee

Oct 2018 – Jun 2019 · 8 mos · Bengaluru Urban, Karnataka, India

  • Trained in scan insertion, ATPG, solving DRCs, Coverage Analysis and debugging, no-timing simulation, JTAG, MBIST

Education

Shri Ramdeobaba Kamla Nehru Engineering College, Katol Road

M.tech — VLSI Design

Jan 2016 – Jan 2018

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