Ramesh mynala — Software Engineer
professional exposure: 1. Have working experience in verifying Ethernet protocol, DMA and arm cortex m4(soc level). 2. Have good knowledge on protocol such as UART, SPI, APB, AHB, AXI and I2C. 3. Coded System Verilog Assertions, Testbench components like scoreboards, environments and agents. 4. Have working knowledge on Gate-level Simulation. 5. Hands on experience in python and perl script
Stackforce AI infers this person is a Design Verification Engineer with expertise in hardware communication protocols and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 10 mos
Skills
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in design verification methodologies.
- Proficient in scripting for automation.
- Strong background in various communication protocols.
Work Experience
MediaTek
Senior Design Verification Engineer (1 yr 3 mos)
Yoctozant Technologies
Asic Design verification engineer (3 yrs 5 mos)
Sandeepani School of VLSI Design
Trainee (1 yr 4 mos)
Education
Bachelor of Technology at Aurora's Scientific Technological And Research Academy
Intermediate at Shivani jr College, Warangal
SSC at ZPPSS
